Lines Matching +full:0 +full:x1740
45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
49 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
72 #define PCI_LEGACY_AUDIO_CTRL 0x40
73 #define SOUND_BLASTER_ENABLE 0x00000001
74 #define FM_SYNTHESIS_ENABLE 0x00000002
75 #define GAME_PORT_ENABLE 0x00000004
76 #define MPU401_IO_ENABLE 0x00000008
77 #define MPU401_IRQ_ENABLE 0x00000010
78 #define ALIAS_10BIT_IO 0x00000020
79 #define SB_DMA_MASK 0x000000C0
80 #define SB_DMA_0 0x00000040
81 #define SB_DMA_1 0x00000040
82 #define SB_DMA_R 0x00000080
83 #define SB_DMA_3 0x000000C0
84 #define SB_IRQ_MASK 0x00000700
85 #define SB_IRQ_5 0x00000000
86 #define SB_IRQ_7 0x00000100
87 #define SB_IRQ_9 0x00000200
88 #define SB_IRQ_10 0x00000300
89 #define MIDI_IRQ_MASK 0x00003800
90 #define SERIAL_IRQ_ENABLE 0x00004000
91 #define DISABLE_LEGACY 0x00008000
93 #define PCI_ALLEGRO_CONFIG 0x50
94 #define SB_ADDR_240 0x00000004
95 #define MPU_ADDR_MASK 0x00000018
96 #define MPU_ADDR_330 0x00000000
97 #define MPU_ADDR_300 0x00000008
98 #define MPU_ADDR_320 0x00000010
99 #define MPU_ADDR_340 0x00000018
100 #define USE_PCI_TIMING 0x00000040
101 #define POSTED_WRITE_ENABLE 0x00000080
102 #define DMA_POLICY_MASK 0x00000700
103 #define DMA_DDMA 0x00000000
104 #define DMA_TDMA 0x00000100
105 #define DMA_PCPCI 0x00000200
106 #define DMA_WBDMA16 0x00000400
107 #define DMA_WBDMA4 0x00000500
108 #define DMA_WBDMA2 0x00000600
109 #define DMA_WBDMA1 0x00000700
110 #define DMA_SAFE_GUARD 0x00000800
111 #define HI_PERF_GP_ENABLE 0x00001000
112 #define PIC_SNOOP_MODE_0 0x00002000
113 #define PIC_SNOOP_MODE_1 0x00004000
114 #define SOUNDBLASTER_IRQ_MASK 0x00008000
115 #define RING_IN_ENABLE 0x00010000
116 #define SPDIF_TEST_MODE 0x00020000
117 #define CLK_MULT_MODE_SELECT_2 0x00040000
118 #define EEPROM_WRITE_ENABLE 0x00080000
119 #define CODEC_DIR_IN 0x00100000
120 #define HV_BUTTON_FROM_GD 0x00200000
121 #define REDUCED_DEBOUNCE 0x00400000
122 #define HV_CTRL_ENABLE 0x00800000
123 #define SPDIF_ENABLE 0x01000000
124 #define CLK_DIV_SELECT 0x06000000
125 #define CLK_DIV_BY_48 0x00000000
126 #define CLK_DIV_BY_49 0x02000000
127 #define CLK_DIV_BY_50 0x04000000
128 #define CLK_DIV_RESERVED 0x06000000
129 #define PM_CTRL_ENABLE 0x08000000
130 #define CLK_MULT_MODE_SELECT 0x30000000
132 #define CLK_MULT_MODE_0 0x00000000
133 #define CLK_MULT_MODE_1 0x10000000
134 #define CLK_MULT_MODE_2 0x20000000
135 #define CLK_MULT_MODE_3 0x30000000
136 #define INT_CLK_SELECT 0x40000000
137 #define INT_CLK_MULT_RESET 0x80000000
140 #define INT_CLK_SRC_NOT_PCI 0x00100000
141 #define INT_CLK_MULT_ENABLE 0x80000000
143 #define PCI_ACPI_CONTROL 0x54
144 #define PCI_ACPI_D0 0x00000000
145 #define PCI_ACPI_D1 0xB4F70000
146 #define PCI_ACPI_D2 0xB4F7B4F7
148 #define PCI_USER_CONFIG 0x58
149 #define EXT_PCI_MASTER_ENABLE 0x00000001
150 #define SPDIF_OUT_SELECT 0x00000002
151 #define TEST_PIN_DIR_CTRL 0x00000004
152 #define AC97_CODEC_TEST 0x00000020
153 #define TRI_STATE_BUFFER 0x00000080
154 #define IN_CLK_12MHZ_SELECT 0x00000100
155 #define MULTI_FUNC_DISABLE 0x00000200
156 #define EXT_MASTER_PAIR_SEL 0x00000400
157 #define PCI_MASTER_SUPPORT 0x00000800
158 #define STOP_CLOCK_ENABLE 0x00001000
159 #define EAPD_DRIVE_ENABLE 0x00002000
160 #define REQ_TRI_STATE_ENABLE 0x00004000
161 #define REQ_LOW_ENABLE 0x00008000
162 #define MIDI_1_ENABLE 0x00010000
163 #define MIDI_2_ENABLE 0x00020000
164 #define SB_AUDIO_SYNC 0x00040000
165 #define HV_CTRL_TEST 0x00100000
166 #define SOUNDBLASTER_TEST 0x00400000
168 #define PCI_USER_CONFIG_C 0x5C
170 #define PCI_DDMA_CTRL 0x60
171 #define DDMA_ENABLE 0x00000001
175 #define HOST_INT_CTRL 0x18
176 #define SB_INT_ENABLE 0x0001
177 #define MPU401_INT_ENABLE 0x0002
178 #define ASSP_INT_ENABLE 0x0010
179 #define RING_INT_ENABLE 0x0020
180 #define HV_INT_ENABLE 0x0040
181 #define CLKRUN_GEN_ENABLE 0x0100
182 #define HV_CTRL_TO_PME 0x0400
183 #define SOFTWARE_RESET_ENABLE 0x8000
188 #define REGB_ENABLE_RESET 0x01
189 #define REGB_STOP_CLOCK 0x10
191 #define HOST_INT_STATUS 0x1A
192 #define SB_INT_PENDING 0x01
193 #define MPU401_INT_PENDING 0x02
194 #define ASSP_INT_PENDING 0x10
195 #define RING_INT_PENDING 0x20
196 #define HV_INT_PENDING 0x40
198 #define HARDWARE_VOL_CTRL 0x1B
199 #define SHADOW_MIX_REG_VOICE 0x1C
200 #define HW_VOL_COUNTER_VOICE 0x1D
201 #define SHADOW_MIX_REG_MASTER 0x1E
202 #define HW_VOL_COUNTER_MASTER 0x1F
204 #define CODEC_COMMAND 0x30
205 #define CODEC_READ_B 0x80
207 #define CODEC_STATUS 0x30
208 #define CODEC_BUSY_B 0x01
210 #define CODEC_DATA 0x32
212 #define RING_BUS_CTRL_A 0x36
213 #define RAC_PME_ENABLE 0x0100
214 #define RAC_SDFS_ENABLE 0x0200
215 #define LAC_PME_ENABLE 0x0400
216 #define LAC_SDFS_ENABLE 0x0800
217 #define SERIAL_AC_LINK_ENABLE 0x1000
218 #define IO_SRAM_ENABLE 0x2000
219 #define IIS_INPUT_ENABLE 0x8000
221 #define RING_BUS_CTRL_B 0x38
222 #define SECOND_CODEC_ID_MASK 0x0003
223 #define SPDIF_FUNC_ENABLE 0x0010
224 #define SECOND_AC_ENABLE 0x0020
225 #define SB_MODULE_INTF_ENABLE 0x0040
226 #define SSPE_ENABLE 0x0040
227 #define M3I_DOCK_ENABLE 0x0080
229 #define SDO_OUT_DEST_CTRL 0x3A
230 #define COMMAND_ADDR_OUT 0x0003
231 #define PCM_LR_OUT_LOCAL 0x0000
232 #define PCM_LR_OUT_REMOTE 0x0004
233 #define PCM_LR_OUT_MUTE 0x0008
234 #define PCM_LR_OUT_BOTH 0x000C
235 #define LINE1_DAC_OUT_LOCAL 0x0000
236 #define LINE1_DAC_OUT_REMOTE 0x0010
237 #define LINE1_DAC_OUT_MUTE 0x0020
238 #define LINE1_DAC_OUT_BOTH 0x0030
239 #define PCM_CLS_OUT_LOCAL 0x0000
240 #define PCM_CLS_OUT_REMOTE 0x0040
241 #define PCM_CLS_OUT_MUTE 0x0080
242 #define PCM_CLS_OUT_BOTH 0x00C0
243 #define PCM_RLF_OUT_LOCAL 0x0000
244 #define PCM_RLF_OUT_REMOTE 0x0100
245 #define PCM_RLF_OUT_MUTE 0x0200
246 #define PCM_RLF_OUT_BOTH 0x0300
247 #define LINE2_DAC_OUT_LOCAL 0x0000
248 #define LINE2_DAC_OUT_REMOTE 0x0400
249 #define LINE2_DAC_OUT_MUTE 0x0800
250 #define LINE2_DAC_OUT_BOTH 0x0C00
251 #define HANDSET_OUT_LOCAL 0x0000
252 #define HANDSET_OUT_REMOTE 0x1000
253 #define HANDSET_OUT_MUTE 0x2000
254 #define HANDSET_OUT_BOTH 0x3000
255 #define IO_CTRL_OUT_LOCAL 0x0000
256 #define IO_CTRL_OUT_REMOTE 0x4000
257 #define IO_CTRL_OUT_MUTE 0x8000
258 #define IO_CTRL_OUT_BOTH 0xC000
260 #define SDO_IN_DEST_CTRL 0x3C
261 #define STATUS_ADDR_IN 0x0003
262 #define PCM_LR_IN_LOCAL 0x0000
263 #define PCM_LR_IN_REMOTE 0x0004
264 #define PCM_LR_RESERVED 0x0008
265 #define PCM_LR_IN_BOTH 0x000C
266 #define LINE1_ADC_IN_LOCAL 0x0000
267 #define LINE1_ADC_IN_REMOTE 0x0010
268 #define LINE1_ADC_IN_MUTE 0x0020
269 #define MIC_ADC_IN_LOCAL 0x0000
270 #define MIC_ADC_IN_REMOTE 0x0040
271 #define MIC_ADC_IN_MUTE 0x0080
272 #define LINE2_DAC_IN_LOCAL 0x0000
273 #define LINE2_DAC_IN_REMOTE 0x0400
274 #define LINE2_DAC_IN_MUTE 0x0800
275 #define HANDSET_IN_LOCAL 0x0000
276 #define HANDSET_IN_REMOTE 0x1000
277 #define HANDSET_IN_MUTE 0x2000
278 #define IO_STATUS_IN_LOCAL 0x0000
279 #define IO_STATUS_IN_REMOTE 0x4000
281 #define SPDIF_IN_CTRL 0x3E
282 #define SPDIF_IN_ENABLE 0x0001
284 #define GPIO_DATA 0x60
285 #define GPIO_DATA_MASK 0x0FFF
286 #define GPIO_HV_STATUS 0x3000
287 #define GPIO_PME_STATUS 0x4000
289 #define GPIO_MASK 0x64
290 #define GPIO_DIRECTION 0x68
291 #define GPO_PRIMARY_AC97 0x0001
292 #define GPI_LINEOUT_SENSE 0x0004
293 #define GPO_SECONDARY_AC97 0x0008
294 #define GPI_VOL_DOWN 0x0010
295 #define GPI_VOL_UP 0x0020
296 #define GPI_IIS_CLK 0x0040
297 #define GPI_IIS_LRCLK 0x0080
298 #define GPI_IIS_DATA 0x0100
299 #define GPI_DOCKING_STATUS 0x0100
300 #define GPI_HEADPHONE_SENSE 0x0200
301 #define GPO_EXT_AMP_SHUTDOWN 0x1000
307 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
309 #define ASSP_INDEX_PORT 0x80
310 #define ASSP_MEMORY_PORT 0x82
311 #define ASSP_DATA_PORT 0x84
313 #define MPU401_DATA_PORT 0x98
314 #define MPU401_STATUS_PORT 0x99
316 #define CLK_MULT_DATA_PORT 0x9C
318 #define ASSP_CONTROL_A 0xA2
319 #define ASSP_0_WS_ENABLE 0x01
320 #define ASSP_CTRL_A_RESERVED1 0x02
321 #define ASSP_CTRL_A_RESERVED2 0x04
322 #define ASSP_CLK_49MHZ_SELECT 0x08
323 #define FAST_PLU_ENABLE 0x10
324 #define ASSP_CTRL_A_RESERVED3 0x20
325 #define DSP_CLK_36MHZ_SELECT 0x40
327 #define ASSP_CONTROL_B 0xA4
328 #define RESET_ASSP 0x00
329 #define RUN_ASSP 0x01
330 #define ENABLE_ASSP_CLOCK 0x00
331 #define STOP_ASSP_CLOCK 0x10
332 #define RESET_TOGGLE 0x40
334 #define ASSP_CONTROL_C 0xA6
335 #define ASSP_HOST_INT_ENABLE 0x01
336 #define FM_ADDR_REMAP_DISABLE 0x02
337 #define HOST_WRITE_PORT_ENABLE 0x08
339 #define ASSP_HOST_INT_STATUS 0xAC
340 #define DSP2HOST_REQ_PIORECORD 0x01
341 #define DSP2HOST_REQ_I2SRATE 0x02
342 #define DSP2HOST_REQ_TIMER 0x04
347 #define DSP_PORT_TIMER_COUNT 0x06
349 #define DSP_PORT_MEMORY_INDEX 0x80
351 #define DSP_PORT_MEMORY_TYPE 0x82
352 #define MEMTYPE_INTERNAL_CODE 0x0002
353 #define MEMTYPE_INTERNAL_DATA 0x0003
354 #define MEMTYPE_MASK 0x0003
356 #define DSP_PORT_MEMORY_DATA 0x84
358 #define DSP_PORT_CONTROL_REG_A 0xA2
359 #define DSP_PORT_CONTROL_REG_B 0xA4
360 #define DSP_PORT_CONTROL_REG_C 0xA6
362 #define REV_A_CODE_MEMORY_BEGIN 0x0000
363 #define REV_A_CODE_MEMORY_END 0x0FFF
364 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
367 #define REV_B_CODE_MEMORY_BEGIN 0x0000
368 #define REV_B_CODE_MEMORY_END 0x0BFF
369 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
372 #define REV_A_DATA_MEMORY_BEGIN 0x1000
373 #define REV_A_DATA_MEMORY_END 0x2FFF
374 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
377 #define REV_B_DATA_MEMORY_BEGIN 0x1000
378 #define REV_B_DATA_MEMORY_END 0x2BFF
379 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
395 #define KDATA_BASE_ADDR 0x1000
396 #define KDATA_BASE_ADDR2 0x1080
398 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
399 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
400 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
401 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
402 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
403 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
404 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
405 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
406 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
408 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
409 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
411 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
412 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
413 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
414 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
415 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
416 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
417 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
418 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
419 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
420 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
422 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
423 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
425 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
426 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
428 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
429 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
431 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
432 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
433 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
435 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
436 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
437 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
438 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
439 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
441 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
442 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
443 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
445 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
446 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
447 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
449 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
450 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
451 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
452 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
453 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
454 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
455 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
456 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
457 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
458 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
460 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
461 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
462 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
464 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
465 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
467 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
468 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
469 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
471 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
472 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
473 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
474 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
475 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
476 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
478 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
479 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
480 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
481 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
482 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
483 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
485 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
486 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
487 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
488 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
489 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
490 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
492 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
493 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
494 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
495 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
497 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
498 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
500 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
501 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
503 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
504 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
505 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
506 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
507 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
509 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
510 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
512 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
513 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
514 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
516 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
517 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
519 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
521 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
522 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
523 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
524 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
525 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
526 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
527 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
528 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
529 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
530 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
531 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
532 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
534 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
535 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
536 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
537 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
539 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
540 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
542 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
543 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
544 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
545 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
547 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
548 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
549 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
550 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
551 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
558 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
559 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
560 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
561 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
562 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
563 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
564 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
565 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
566 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
567 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
568 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
569 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
570 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
571 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
572 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
573 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
575 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
576 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
577 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
578 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
579 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
580 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
581 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
582 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
583 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
584 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
585 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
587 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
588 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
589 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
590 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
591 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
592 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
602 #define CDATA_INSTANCE_READY 0x00
604 #define CDATA_HOST_SRC_ADDRL 0x01
605 #define CDATA_HOST_SRC_ADDRH 0x02
606 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
607 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
608 #define CDATA_HOST_SRC_CURRENTL 0x05
609 #define CDATA_HOST_SRC_CURRENTH 0x06
611 #define CDATA_IN_BUF_CONNECT 0x07
612 #define CDATA_OUT_BUF_CONNECT 0x08
614 #define CDATA_IN_BUF_BEGIN 0x09
615 #define CDATA_IN_BUF_END_PLUS_1 0x0A
616 #define CDATA_IN_BUF_HEAD 0x0B
617 #define CDATA_IN_BUF_TAIL 0x0C
618 #define CDATA_OUT_BUF_BEGIN 0x0D
619 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
620 #define CDATA_OUT_BUF_HEAD 0x0F
621 #define CDATA_OUT_BUF_TAIL 0x10
623 #define CDATA_DMA_CONTROL 0x11
624 #define CDATA_RESERVED 0x12
626 #define CDATA_FREQUENCY 0x13
627 #define CDATA_LEFT_VOLUME 0x14
628 #define CDATA_RIGHT_VOLUME 0x15
629 #define CDATA_LEFT_SUR_VOL 0x16
630 #define CDATA_RIGHT_SUR_VOL 0x17
632 #define CDATA_HEADER_LEN 0x18
643 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
644 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
647 #define MINISRC_COEF_LOC 0x175
649 #define DMACONTROL_BLOCK_MASK 0x000F
650 #define DMAC_BLOCK0_SELECTOR 0x0000
651 #define DMAC_BLOCK1_SELECTOR 0x0001
652 #define DMAC_BLOCK2_SELECTOR 0x0002
653 #define DMAC_BLOCK3_SELECTOR 0x0003
654 #define DMAC_BLOCK4_SELECTOR 0x0004
655 #define DMAC_BLOCK5_SELECTOR 0x0005
656 #define DMAC_BLOCK6_SELECTOR 0x0006
657 #define DMAC_BLOCK7_SELECTOR 0x0007
658 #define DMAC_BLOCK8_SELECTOR 0x0008
659 #define DMAC_BLOCK9_SELECTOR 0x0009
660 #define DMAC_BLOCKA_SELECTOR 0x000A
661 #define DMAC_BLOCKB_SELECTOR 0x000B
662 #define DMAC_BLOCKC_SELECTOR 0x000C
663 #define DMAC_BLOCKD_SELECTOR 0x000D
664 #define DMAC_BLOCKE_SELECTOR 0x000E
665 #define DMAC_BLOCKF_SELECTOR 0x000F
666 #define DMACONTROL_PAGE_MASK 0x00F0
667 #define DMAC_PAGE0_SELECTOR 0x0030
668 #define DMAC_PAGE1_SELECTOR 0x0020
669 #define DMAC_PAGE2_SELECTOR 0x0010
670 #define DMAC_PAGE3_SELECTOR 0x0000
671 #define DMACONTROL_AUTOREPEAT 0x1000
672 #define DMACONTROL_STOPPED 0x2000
673 #define DMACONTROL_DIRECTION 0x0100
678 * range is a little less insane. 0x7fff is
681 #define ARB_VOLUME ( 0x6800 )
748 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
783 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
785 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
787 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
789 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
791 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
793 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
795 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
797 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
798 {0,},
804 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
805 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
806 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
807 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
808 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
813 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
814 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
815 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
822 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
823 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
824 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
825 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
826 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
827 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
828 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
829 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
830 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
831 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
832 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
833 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
834 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
835 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
836 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
837 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
838 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
839 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
840 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
841 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
842 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
843 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
844 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
845 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
846 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
847 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
849 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
851 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
853 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
855 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
857 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
859 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
861 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
863 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
865 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
867 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
869 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
871 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
872 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
873 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
874 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
875 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
877 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
878 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
879 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
880 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
881 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
882 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
883 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
884 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
885 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
886 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
887 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
888 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
889 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
890 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
891 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
892 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
893 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
899 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
900 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
961 * internally that must be packed.. 0 terminates,
963 * to be 0, the lists have static lengths set
990 0); in snd_m3_remove_list()
1017 if (chip->timer_users > 0) in snd_m3_dec_timer_users()
1022 0); in snd_m3_dec_timer_users()
1026 0); in snd_m3_dec_timer_users()
1061 return 0; in snd_m3_pcm_start()
1072 s->inst.data + CDATA_INSTANCE_READY, 0); in snd_m3_pcm_stop()
1083 KDATA_ADC1_REQUEST, 0); in snd_m3_pcm_stop()
1086 return 0; in snd_m3_pcm_stop()
1113 err = 0; /* should return error? */ in snd_m3_pcm_trigger()
1115 s->running = 0; in snd_m3_pcm_trigger()
1134 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); in snd_m3_pcm_setup1()
1135 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); in snd_m3_pcm_setup1()
1137 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); in snd_m3_pcm_setup1()
1138 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); in snd_m3_pcm_setup1()
1145 s->hwptr = 0; in snd_m3_pcm_setup1()
1146 s->count = 0; in snd_m3_pcm_setup1()
1148 #define LO(x) ((x) & 0xffff) in snd_m3_pcm_setup1()
1222 s->index[0] = snd_m3_add_list(chip, s->index_list[0], in snd_m3_pcm_setup2()
1234 runtime->channels == 2 ? 0 : 1); in snd_m3_pcm_setup2()
1238 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); in snd_m3_pcm_setup2()
1256 {SRC3_DIRECTION_OFFSET, 0} ,
1258 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1259 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1260 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1261 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1262 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1263 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1264 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1265 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1266 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1267 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1268 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1269 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1273 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1274 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1300 subs->runtime->rate > 45000 ? 0xff : 0); in snd_m3_playback_setup()
1310 for (i = 0; i < ARRAY_SIZE(pv); i++) in snd_m3_playback_setup()
1325 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1326 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1327 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1328 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1329 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1330 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1331 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1332 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1333 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1334 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1335 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1336 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1339 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1340 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1341 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1342 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1343 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1368 for (i = 0; i < ARRAY_SIZE(rv); i++) in snd_m3_capture_setup()
1380 if (s->buffer_addr & 0x3) { in snd_m3_pcm_hw_params()
1382 s->buffer_addr = s->buffer_addr & ~0x3; in snd_m3_pcm_hw_params()
1384 return 0; in snd_m3_pcm_hw_params()
1392 return 0; in snd_m3_pcm_hw_free()
1394 s->buffer_addr = 0; in snd_m3_pcm_hw_free()
1395 return 0; in snd_m3_pcm_hw_free()
1428 return 0; in snd_m3_pcm_prepare()
1437 u16 hi = 0, lo = 0; in snd_m3_get_pointer()
1467 return 0; in snd_m3_pcm_pointer()
1516 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1525 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; in snd_m3_update_hw_volume()
1530 4 so writing 0x88 is not strictly necessary in snd_m3_update_hw_volume()
1536 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); in snd_m3_update_hw_volume()
1537 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); in snd_m3_update_hw_volume()
1538 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); in snd_m3_update_hw_volume()
1539 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); in snd_m3_update_hw_volume()
1552 case 0x88: in snd_m3_update_hw_volume()
1556 val ^= 0x8000; in snd_m3_update_hw_volume()
1558 case 0xaa: in snd_m3_update_hw_volume()
1560 if ((val & 0x7f) > 0) in snd_m3_update_hw_volume()
1562 if ((val & 0x7f00) > 0) in snd_m3_update_hw_volume()
1563 val -= 0x0100; in snd_m3_update_hw_volume()
1565 case 0x66: in snd_m3_update_hw_volume()
1567 if ((val & 0x7f) < 0x1f) in snd_m3_update_hw_volume()
1569 if ((val & 0x7f00) < 0x1f00) in snd_m3_update_hw_volume()
1570 val += 0x0100; in snd_m3_update_hw_volume()
1580 val = 0; in snd_m3_update_hw_volume()
1582 case 0x88: in snd_m3_update_hw_volume()
1588 case 0xaa: in snd_m3_update_hw_volume()
1592 case 0x66: in snd_m3_update_hw_volume()
1601 input_report_key(chip->input_dev, val, 0); in snd_m3_update_hw_volume()
1615 if (status == 0xff) in snd_m3_interrupt()
1633 for (i = 0; i < chip->num_substreams; i++) { in snd_m3_interrupt()
1643 #if 0 /* TODO: not supported yet */ in snd_m3_interrupt()
1711 for (i = 0; i < chip->num_substreams; i++) { in snd_m3_substream_open()
1720 s->running = 0; in snd_m3_substream_open()
1728 s->index_list[0] = &chip->mixer_list; in snd_m3_substream_open()
1730 s->index_list[0] = &chip->adc1_list; in snd_m3_substream_open()
1734 return 0; in snd_m3_substream_open()
1749 snd_m3_remove_list(chip, s->index_list[0], s->index[0]); in snd_m3_substream_close()
1752 s->in_lists = 0; in snd_m3_substream_close()
1754 s->running = 0; in snd_m3_substream_close()
1755 s->opened = 0; in snd_m3_substream_close()
1767 if (err < 0) in snd_m3_playback_open()
1772 return 0; in snd_m3_playback_open()
1781 return 0; in snd_m3_playback_close()
1792 if (err < 0) in snd_m3_capture_open()
1797 return 0; in snd_m3_capture_open()
1806 return 0; in snd_m3_capture_close()
1841 if (err < 0) in snd_m3_pcm()
1848 pcm->info_flags = 0; in snd_m3_pcm()
1855 return 0; in snd_m3_pcm()
1872 if (! (snd_m3_inb(chip, 0x30) & 1)) in snd_m3_ac97_wait()
1873 return 0; in snd_m3_ac97_wait()
1875 } while (i-- > 0); in snd_m3_ac97_wait()
1885 unsigned short data = 0xffff; in snd_m3_ac97_read()
1889 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); in snd_m3_ac97_read()
1905 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); in snd_m3_ac97_write()
1911 if (ac97->id == 0x45838308 && reg == AC97_MASTER) { in snd_m3_ac97_write()
1914 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); in snd_m3_ac97_write()
1924 isremote = isremote ? 1 : 0; in snd_m3_remote_codec_config()
1928 if (chip->pci->subsystem_vendor == 0x1028 && in snd_m3_remote_codec_config()
1929 chip->pci->subsystem_device == 0x00e5) in snd_m3_remote_codec_config()
1948 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); in snd_m3_try_read_vendor()
1953 ret = snd_m3_inw(chip, 0x32); in snd_m3_try_read_vendor()
1955 return (ret == 0) || (ret == 0xffff); in snd_m3_try_read_vendor()
1961 int delay1 = 0, delay2 = 0, i; in snd_m3_ac97_reset()
1978 for (i = 0; i < 5; i++) { in snd_m3_ac97_reset()
1981 dir |= 0x10; /* assuming pci bus master? */ in snd_m3_ac97_reset()
1983 snd_m3_remote_codec_config(chip, 0); in snd_m3_ac97_reset()
1990 outw(0, io + GPIO_DATA); in snd_m3_ac97_reset()
1999 outw(~0, io + GPIO_MASK); in snd_m3_ac97_reset()
2014 #if 0 in snd_m3_ac97_reset()
2036 err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus); in snd_m3_mixer()
2037 if (err < 0) in snd_m3_mixer()
2040 memset(&ac97, 0, sizeof(ac97)); in snd_m3_mixer()
2043 if (err < 0) in snd_m3_mixer()
2047 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); in snd_m3_mixer()
2049 snd_ac97_write(chip->ac97, AC97_PCM, 0); in snd_m3_mixer()
2058 return 0; in snd_m3_mixer()
2068 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2069 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2078 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) in snd_m3_assp_init()
2080 KDATA_BASE_ADDR + i, 0); in snd_m3_assp_init()
2083 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) in snd_m3_assp_init()
2085 KDATA_BASE_ADDR2 + i, 0); in snd_m3_assp_init()
2094 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { in snd_m3_assp_init()
2101 * We only have this one client and we know that 0x400 in snd_m3_assp_init()
2107 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { in snd_m3_assp_init()
2109 0x400 + i, le16_to_cpu(data[i])); in snd_m3_assp_init()
2115 for (i = 0; i < MINISRC_LPF_LEN ; i++) { in snd_m3_assp_init()
2117 0x400 + MINISRC_COEF_LOC + i, in snd_m3_assp_init()
2122 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, in snd_m3_assp_init()
2123 0x8000); in snd_m3_assp_init()
2131 0x400); in snd_m3_assp_init()
2138 KDATA_MIXER_TASK_NUMBER,0); in snd_m3_assp_init()
2148 chip->mixer_list.curlen = 0; in snd_m3_assp_init()
2151 chip->adc1_list.curlen = 0; in snd_m3_assp_init()
2154 chip->dma_list.curlen = 0; in snd_m3_assp_init()
2157 chip->msrc_list.curlen = 0; in snd_m3_assp_init()
2171 * the revb memory map has 0x1100 through 0x1c00 in snd_m3_assp_client_init()
2181 address = 0x1100 + ((data_bytes/2) * index); in snd_m3_assp_client_init()
2183 if ((address + (data_bytes/2)) >= 0x1c00) { in snd_m3_assp_client_init()
2185 "no memory for %d bytes at ind %d (addr 0x%x)\n", in snd_m3_assp_client_init()
2191 s->inst.code = 0x400; in snd_m3_assp_client_init()
2194 for (i = data_bytes / 2; i > 0; address++, i--) { in snd_m3_assp_client_init()
2196 address, 0); in snd_m3_assp_client_init()
2199 return 0; in snd_m3_assp_client_init()
2218 polarity = enable ? 0 : 1; in snd_m3_amp_enable()
2230 outw(0xffff, io + GPIO_MASK); in snd_m3_amp_enable()
2246 outw(0xffff, io + GPIO_MASK); in snd_m3_hv_init()
2247 outw(0x0000, io + GPIO_DATA); in snd_m3_hv_init()
2253 outw(0xffff, io + GPIO_MASK); in snd_m3_hv_init()
2304 outb(0x00, io + HARDWARE_VOL_CTRL); in snd_m3_chip_init()
2305 outb(0x88, io + SHADOW_MIX_REG_VOICE); in snd_m3_chip_init()
2306 outb(0x88, io + HW_VOL_COUNTER_VOICE); in snd_m3_chip_init()
2307 outb(0x88, io + SHADOW_MIX_REG_MASTER); in snd_m3_chip_init()
2308 outb(0x88, io + HW_VOL_COUNTER_MASTER); in snd_m3_chip_init()
2310 return 0; in snd_m3_chip_init()
2343 for (i = 0; i < chip->num_substreams; i++) { in snd_m3_free()
2352 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ in snd_m3_free()
2371 return 0; in m3_suspend()
2383 dsp_index = 0; in m3_suspend()
2390 return 0; in m3_suspend()
2400 return 0; in m3_resume()
2403 snd_m3_outw(chip, 0, 0x54); in m3_resume()
2404 snd_m3_outw(chip, 0, 0x56); in m3_resume()
2411 dsp_index = 0; in m3_resume()
2421 KDATA_DMA_ACTIVE, 0); in m3_resume()
2433 chip->in_suspend = 0; in m3_resume()
2434 return 0; in m3_resume()
2469 return 0; in snd_m3_input_register()
2513 if (amp_gpio >= 0 && amp_gpio <= 0x0f) in snd_m3_create()
2547 if (err < 0) in snd_m3_create()
2552 if (err < 0) in snd_m3_create()
2556 if (err < 0) in snd_m3_create()
2559 chip->iobase = pci_resource_start(pci, 0); in snd_m3_create()
2591 if (err < 0) in snd_m3_create()
2594 for (i = 0; i < chip->num_substreams; i++) { in snd_m3_create()
2597 if (err < 0) in snd_m3_create()
2601 err = snd_m3_pcm(chip, 0); in snd_m3_create()
2602 if (err < 0) in snd_m3_create()
2618 return 0; in snd_m3_create()
2632 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) in __snd_m3_probe()
2644 if (err < 0) in __snd_m3_probe()
2663 if (err < 0) in __snd_m3_probe()
2667 sprintf(card->longname, "%s at 0x%lx, irq %d", in __snd_m3_probe()
2671 if (err < 0) in __snd_m3_probe()
2674 #if 0 /* TODO: not supported yet */ in __snd_m3_probe()
2676 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, in __snd_m3_probe()
2680 if (err < 0) in __snd_m3_probe()
2686 return 0; in __snd_m3_probe()