Lines Matching full:byte

41 #define VT1724_REG_CONTROL		0x00	/* byte */
43 #define VT1724_REG_IRQMASK		0x01	/* byte */
47 #define VT1724_REG_IRQSTAT		0x02	/* byte */
49 #define VT1724_REG_SYS_CFG		0x04	/* byte - system configuration PCI60 on Envy24*/
58 #define VT1724_REG_AC97_CFG		0x05	/* byte */
62 #define VT1724_REG_I2S_FEATURES		0x06	/* byte */
69 #define VT1724_REG_SPDIF_CFG		0x07	/* byte */
77 //#define VT1724_REG_AC97_INDEX		0x08	/* byte */
78 //#define VT1724_REG_AC97_CMD		0x09	/* byte */
80 #define VT1724_REG_MPU_TXFIFO		0x0a	/*byte ro. number of bytes in TX fifo*/
81 #define VT1724_REG_MPU_RXFIFO		0x0b	/*byte ro. number of bytes in RX fifo*/
83 #define VT1724_REG_MPU_DATA		0x0c	/* byte */
84 #define VT1724_REG_MPU_CTRL		0x0d	/* byte */
91 #define VT1724_REG_MPU_FIFO_WM	0x0e	/*byte set the high/low watermarks for RX/TX fifos*/
95 #define VT1724_REG_I2C_DEV_ADDR	0x10	/* byte */
97 #define VT1724_REG_I2C_BYTE_ADDR	0x11	/* byte */
98 #define VT1724_REG_I2C_DATA		0x12	/* byte */
99 #define VT1724_REG_I2C_CTRL		0x13	/* byte */
109 #define VT1724_REG_GPIO_DATA_22	0x1e /* byte direction for GPIO 16:22 */
110 #define VT1724_REG_GPIO_WRITE_MASK_22	0x1f /* byte write mask for GPIO 16:22 */
119 #define VT1724_MT_IRQ			0x00	/* byte - interrupt mask */
129 #define VT1724_MT_RATE			0x01	/* byte - sampling rate select */
131 #define VT1724_MT_I2S_FORMAT		0x02	/* byte - I2S data format */
135 #define VT1724_MT_DMA_INT_MASK		0x03	/* byte -DMA Interrupt Mask */
137 #define VT1724_MT_AC97_INDEX		0x04	/* byte - AC'97 index */
138 #define VT1724_MT_AC97_CMD		0x05	/* byte - AC'97 command & status */
148 #define VT1724_MT_DMA_CONTROL		0x18	/* byte - control */
185 #define VT1724_MT_MONITOR_PEAKINDEX	0x3e	/* byte */
186 #define VT1724_MT_MONITOR_PEAKDATA	0x3f	/* byte */