Lines Matching +full:0 +full:x44200000
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x80
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
70 #define SCP_SET 0
107 #define VNODE_START_NID 0x80
117 #define EFFECT_START_NID 0x90
170 #define DSP_CAPTURE_INIT_LATENCY 0
181 int direct; /* 0:output; 1:input*/
187 #define EFX_DIR_OUT 0
193 .mid = 0x96,
194 .reqs = {0, 1},
197 .def_vals = {0x3F800000, 0x3F2B851F}
201 .mid = 0x96,
205 .def_vals = {0x3F800000, 0x3F266666}
209 .mid = 0x96,
213 .def_vals = {0x00000000, 0x3F000000}
217 .mid = 0x96,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
225 .mid = 0x96,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
233 .mid = 0x96,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
252 .mid = 0x95,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
260 .mid = 0x95,
264 .def_vals = {0x00000000, 0x3F3D70A4}
268 .mid = 0x95,
272 .def_vals = {0x3F800000, 0x3F000000}
276 .mid = 0x95,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
290 #define TUNING_CTL_START_NID 0xC0
313 int direct; /* 0:output; 1:input*/
321 .mid = 0x95,
324 .def_val = 0x41F00000
329 .mid = 0x95,
332 .def_val = 0x3F3D70A4
337 .mid = 0x96,
340 .def_val = 0x00000000
345 .mid = 0x96,
348 .def_val = 0x00000000
353 .mid = 0x96,
356 .def_val = 0x00000000
361 .mid = 0x96,
364 .def_val = 0x00000000
369 .mid = 0x96,
372 .def_val = 0x00000000
377 .mid = 0x96,
380 .def_val = 0x00000000
385 .mid = 0x96,
388 .def_val = 0x00000000
393 .mid = 0x96,
396 .def_val = 0x00000000
401 .mid = 0x96,
404 .def_val = 0x00000000
409 .mid = 0x96,
412 .def_val = 0x00000000
435 .mid = 0x95,
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
531 .mid = 0x96,
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
619 * module ID 0x96, the output effects module.
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
709 #define DSP_VOL_OUT 0
720 .mid = 0x32,
724 .mid = 0x37,
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
781 .val = 0xa0
784 .val = 0xc0
787 .val = 0x80
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
895 CONTROL_FLAG_C_MGR = 0,
952 /* 0: None, 1: Mic1In*/
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1040 SR_COUNT = 0x10,
1042 SR_RATE_UNKNOWN = 0x1F
1047 DSP_DOWNLOAD_INIT = 0,
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1194 { 0x0c, 0x411111f0 }, /* N/A */
1195 { 0x0d, 0x411111f0 }, /* N/A */
1196 { 0x0e, 0x411111f0 }, /* N/A */
1197 { 0x0f, 0x0321101f }, /* HP */
1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1199 { 0x11, 0x03a11021 }, /* Mic */
1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1201 { 0x13, 0x411111f0 }, /* N/A */
1202 { 0x18, 0x411111f0 }, /* N/A */
1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1210 { 0x0d, 0x014510f0 }, /* Digital Out */
1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1216 { 0x13, 0x908700f0 }, /* What U Hear In*/
1217 { 0x18, 0x50d000f0 }, /* N/A */
1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1225 { 0x0d, 0x014510f0 }, /* Digital Out */
1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1231 { 0x13, 0x908700f0 }, /* What U Hear In*/
1232 { 0x18, 0x50d000f0 }, /* N/A */
1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1240 { 0x0d, 0x014510f0 }, /* Digital Out */
1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1246 { 0x13, 0x908700f0 }, /* What U Hear In*/
1247 { 0x18, 0x50d000f0 }, /* N/A */
1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1255 { 0x0d, 0x014510f0 }, /* Digital Out */
1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1261 { 0x13, 0x908700f0 }, /* What U Hear In*/
1262 { 0x18, 0x50d000f0 }, /* N/A */
1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1270 { 0x0d, 0x014510f0 }, /* Digital Out */
1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1276 { 0x13, 0x908700f0 }, /* What U Hear In*/
1277 { 0x18, 0x500000f0 }, /* N/A */
1282 { 0x0b, 0x01017010 },
1283 { 0x0c, 0x014510f0 },
1284 { 0x0d, 0x414510f0 },
1285 { 0x0e, 0x01c520f0 },
1286 { 0x0f, 0x01017114 },
1287 { 0x10, 0x01017011 },
1288 { 0x11, 0x018170ff },
1289 { 0x12, 0x01a170f0 },
1290 { 0x13, 0x908700f0 },
1291 { 0x18, 0x500000f0 },
1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1335 unsigned int dac2port; /* ParamID 0x0d value. */
1370 { .dac2port = 0x24,
1374 .mmio_gpio_count = 0,
1375 .scp_cmds_count = 0,
1379 { .dac2port = 0x21,
1382 .hda_gpio_set = 0,
1383 .mmio_gpio_count = 0,
1384 .scp_cmds_count = 0,
1393 { .dac2port = 0x24,
1398 .scp_cmds_count = 0,
1402 { .dac2port = 0x21,
1406 .mmio_gpio_set = { 0 },
1407 .scp_cmds_count = 0,
1416 { .dac2port = 0x18,
1420 .mmio_gpio_set = { 0, 1, 1 },
1421 .scp_cmds_count = 0,
1424 { .dac2port = 0x12,
1428 .mmio_gpio_set = { 1, 1, 0 },
1429 .scp_cmds_count = 0,
1438 { .dac2port = 0x24,
1442 .mmio_gpio_set = { 1, 1, 0 },
1443 .scp_cmds_count = 0,
1447 { .dac2port = 0x21,
1451 .mmio_gpio_set = { 0, 1, 1 },
1452 .scp_cmds_count = 0,
1461 { .dac2port = 0xa4,
1463 .mmio_gpio_count = 0,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000012
1474 { .dac2port = 0xa1,
1476 .mmio_gpio_count = 0,
1478 .scp_cmd_mid = { 0x96, 0x96 },
1483 .chipio_write_addr = 0x0018b03c,
1484 .chipio_write_data = 0x00000012
1492 { .dac2port = 0x58,
1495 .mmio_gpio_pin = { 0 },
1498 .scp_cmd_mid = { 0x96, 0x96 },
1503 .chipio_write_addr = 0x0018b03c,
1504 .chipio_write_data = 0x00000000
1507 { .dac2port = 0x58,
1510 .mmio_gpio_pin = { 0 },
1513 .scp_cmd_mid = { 0x96, 0x96 },
1518 .chipio_write_addr = 0x0018b03c,
1519 .chipio_write_data = 0x00000010
1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1534 return ((response == -1) ? -1 : 0);
1541 converter_format & 0xffff, res);
1548 unsigned char converter_stream_channel = 0;
1550 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1568 return 0;
1585 return 0;
1589 chip_addx & 0xffff);
1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1622 (spec->curr_chip_addx + 4) : ~0U;
1633 int status = 0;
1640 while ((count-- != 0) && (status == 0))
1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1667 0);
1673 (spec->curr_chip_addx + 4) : ~0U;
1691 if (err < 0)
1695 if (err < 0)
1715 if (err < 0)
1719 if (err < 0)
1740 if (status < 0)
1764 if (err < 0)
1768 if (err < 0)
1786 flag_bit = (flag_state ? 1 : 0);
1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1807 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1811 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1829 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1832 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1833 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1889 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1920 * 0x80-0xFF.
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1933 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1934 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1936 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1944 tmp = addr & 0xff;
1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1949 tmp = (addr >> 8) & 0xff;
1950 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1957 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1963 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1964 VENDOR_CHIPIO_8051_DATA_READ, 0);
1971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1972 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
2010 chipio_8051_set_address(codec, addr & 0xff);
2019 chipio_8051_set_address(codec, addr & 0xff);
2032 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2033 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2034 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2050 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2051 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2068 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2069 VENDOR_DSPIO_STATUS, 0);
2089 scp_data & 0xffff);
2090 if (status < 0)
2095 if (status < 0)
2099 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2100 VENDOR_DSPIO_STATUS, 0);
2105 -EIO : 0;
2114 int status = 0;
2120 count = 0;
2123 if (status != 0)
2135 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2139 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2144 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2145 VENDOR_DSPIO_SCP_READ_DATA, 0);
2147 return 0;
2153 int status = 0;
2162 count = 0;
2165 if (status != 0)
2171 if (status == 0) {
2174 if (status != 0)
2193 unsigned int header = 0;
2195 header = (data_size & 0x1f) << 27;
2196 header |= (error_flag & 0x01) << 26;
2197 header |= (resp_flag & 0x01) << 25;
2198 header |= (device_flag & 0x01) << 24;
2199 header |= (req & 0x7f) << 17;
2200 header |= (get_flag & 0x01) << 16;
2201 header |= (source_id & 0xff) << 8;
2202 header |= target_id & 0xff;
2218 *data_size = (header >> 27) & 0x1f;
2220 *error_flag = (header >> 26) & 0x01;
2222 *resp_flag = (header >> 25) & 0x01;
2224 *device_flag = (header >> 24) & 0x01;
2226 *req = (header >> 17) & 0x7f;
2228 *get_flag = (header >> 16) & 0x01;
2230 *source_id = (header >> 8) & 0xff;
2232 *target_id = header & 0xff;
2246 unsigned int dummy = 0;
2252 } while (status == 0 && time_before(jiffies, timeout));
2258 unsigned int data = 0;
2261 if (dspio_read(codec, &data) < 0)
2264 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2270 return 0;
2288 unsigned int scp_send_size = 0;
2297 *bytes_returned = 0;
2318 spec->wait_scp_header &= 0xffff0000;
2327 if (status < 0) {
2328 spec->wait_scp = 0;
2334 memset(return_buf, 0, return_buf_size);
2345 status = 0;
2349 spec->wait_scp = 0;
2373 int status = 0;
2379 memset(&scp_send, 0, sizeof(scp_send));
2380 memset(&scp_reply, 0, sizeof(scp_reply));
2382 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2390 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2396 0, 0, 0, len/sizeof(unsigned int));
2397 if (data != NULL && len > 0) {
2402 ret_bytes = 0;
2408 if (status < 0) {
2421 return 0;
2461 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2470 int status = 0;
2474 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2475 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2478 if (status < 0) {
2483 if ((*dma_chan + 1) == 0) {
2499 int status = 0;
2500 unsigned int dummy = 0;
2505 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2509 if (status < 0) {
2529 if (err < 0)
2535 if (halt_state != 0) {
2540 if (err < 0)
2547 if (err < 0)
2551 return 0;
2564 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2573 return 0;
2607 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2616 int status = 0;
2642 active = 0;
2650 if (status < 0) {
2665 if (status < 0) {
2675 if (status < 0) {
2686 if (status < 0) {
2695 if (status < 0) {
2703 if (status < 0) {
2710 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2711 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2717 return 0;
2728 int status = 0;
2735 unsigned int dma_cfg = 0;
2736 unsigned int adr_ofs = 0;
2737 unsigned int xfr_cnt = 0;
2757 incr_field = 0;
2770 if (status < 0) {
2777 (code ? 0 : 1));
2781 if (status < 0) {
2795 if (status < 0) {
2802 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2803 "ADROFS=0x%x, XFRCNT=0x%x\n",
2808 return 0;
2817 unsigned int reg = 0;
2818 int status = 0;
2826 if (status < 0) {
2838 if (status < 0) {
2853 unsigned int reg = 0;
2854 int status = 0;
2862 if (status < 0) {
2873 if (status < 0) {
2899 int status = 0;
2903 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2904 if (status < 0)
2911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2920 if (status < 0)
2923 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2924 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2928 return (res < 0) ? res : 0;
2936 int status = 0;
2938 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2939 if (status < 0)
2942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2946 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2968 rate_multi, 0, port_map);
2981 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
3005 if (status < 0) {
3026 DMA_STATE_STOP = 0,
3042 return 0;
3061 if (status < 0)
3064 return 0;
3079 return 0;
3083 return 0;
3101 return 0;
3126 static const u32 g_magic_value = 0x4c46584d;
3127 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3141 return p->count == 0;
3158 #define INVALID_DMA_CHANNEL (~0U)
3180 status = chipio_write(codec, data[0], data[1]);
3181 if (status < 0) {
3188 return 0;
3196 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3213 int status = 0;
3245 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3255 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3257 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3277 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3281 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3284 if (hda_frame_size_words == 0) {
3294 "chpadr=0x%08x frmsz=%u nchan=%u "
3312 while (words_to_write != 0) {
3319 if (status < 0)
3323 if (status < 0)
3330 if (status < 0)
3333 if (status < 0)
3340 if (status < 0)
3342 if (remainder_words != 0) {
3347 if (status < 0)
3349 remainder_words = 0;
3353 if (status < 0)
3372 if (status < 0)
3380 if (remainder_words != 0) {
3393 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3410 unsigned short hda_format = 0;
3412 unsigned char stream_id = 0;
3436 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3441 if (status < 0) {
3450 if (status < 0)
3456 if (status < 0) {
3463 port_map_mask = 0;
3466 if (status < 0) {
3473 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3474 if (status < 0) {
3488 if (status < 0)
3498 if (port_map_mask != 0)
3501 if (status < 0)
3505 WIDGET_CHIP_CTRL, 0, 0, &response);
3528 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3529 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3532 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3542 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3545 * @router_chans: number of audio router channels to be allocated (0 means use
3561 int status = 0;
3566 if (router_chans == 0) {
3586 if (status < 0)
3593 if (status < 0)
3603 } while (0);
3611 unsigned int data = 0;
3612 int status = 0;
3614 status = chipio_read(codec, 0x40004, &data);
3615 if ((status < 0) || (data != 1))
3648 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3661 gpio_data = gpio_pin & 0xF;
3662 gpio_data |= ((enable << 8) & 0x100);
3664 writew(gpio_data, spec->mem_base + 0x320);
3681 writel(0x0000007e, spec->mem_base + 0x210);
3682 readl(spec->mem_base + 0x210);
3683 writel(0x0000005a, spec->mem_base + 0x210);
3684 readl(spec->mem_base + 0x210);
3685 readl(spec->mem_base + 0x210);
3687 writel(0x00800005, spec->mem_base + 0x20c);
3688 writel(group, spec->mem_base + 0x804);
3690 writel(0x00800005, spec->mem_base + 0x20c);
3691 write_val = (target & 0xff);
3695 writel(write_val, spec->mem_base + 0x204);
3701 readl(spec->mem_base + 0x860);
3702 readl(spec->mem_base + 0x854);
3703 readl(spec->mem_base + 0x840);
3705 writel(0x00800004, spec->mem_base + 0x20c);
3706 writel(0x00000000, spec->mem_base + 0x210);
3707 readl(spec->mem_base + 0x210);
3708 readl(spec->mem_base + 0x210);
3720 writel(0x0000007e, spec->mem_base + 0x210);
3721 readl(spec->mem_base + 0x210);
3722 writel(0x0000005a, spec->mem_base + 0x210);
3723 readl(spec->mem_base + 0x210);
3724 readl(spec->mem_base + 0x210);
3726 writel(0x00800003, spec->mem_base + 0x20c);
3727 writel(group, spec->mem_base + 0x804);
3729 writel(0x00800005, spec->mem_base + 0x20c);
3730 write_val = (target & 0xff);
3734 writel(write_val, spec->mem_base + 0x204);
3736 readl(spec->mem_base + 0x860);
3737 readl(spec->mem_base + 0x854);
3738 readl(spec->mem_base + 0x840);
3740 writel(0x00800004, spec->mem_base + 0x20c);
3741 writel(0x00000000, spec->mem_base + 0x210);
3742 readl(spec->mem_base + 0x210);
3743 readl(spec->mem_base + 0x210);
3762 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3763 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3764 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3767 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3768 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3783 snd_hda_codec_write(codec, 0x01, 0,
3784 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3785 snd_hda_codec_write(codec, 0x01, 0,
3786 AC_VERB_SET_GPIO_MASK, 0x07);
3787 snd_hda_codec_write(codec, 0x01, 0,
3788 AC_VERB_SET_GPIO_DATA, 0x04);
3789 snd_hda_codec_write(codec, 0x01, 0,
3790 AC_VERB_SET_GPIO_DATA, 0x06);
3793 snd_hda_codec_write(codec, 0x01, 0,
3794 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3795 snd_hda_codec_write(codec, 0x01, 0,
3796 AC_VERB_SET_GPIO_MASK, 0x1F);
3797 snd_hda_codec_write(codec, 0x01, 0,
3798 AC_VERB_SET_GPIO_DATA, 0x0C);
3810 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3812 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3827 /* Set GPIO bit 1 to 0 for rear mic */
3828 R3DI_REAR_MIC = 0,
3834 /* Set GPIO bit 2 to 0 for headphone */
3835 R3DI_HEADPHONE_OUT = 0,
3841 R3DI_DSP_DOWNLOADING = 0,
3853 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3863 snd_hda_codec_write(codec, codec->core.afg, 0,
3873 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3878 snd_hda_codec_write(codec, codec->core.afg, 0,
3882 /* Set DOWNLOADING bit to 0. */
3885 snd_hda_codec_write(codec, codec->core.afg, 0,
3892 snd_hda_codec_write(codec, codec->core.afg, 0,
3907 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3909 return 0;
3919 return 0;
3926 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3928 return 0;
3940 return 0;
4004 stream_tag, 0, format);
4006 return 0;
4016 return 0;
4019 return 0;
4031 return 0;
4057 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4075 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4084 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4104 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4105 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4106 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4107 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4108 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4109 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4110 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4111 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4112 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4113 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4114 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4115 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4116 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4117 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4118 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4119 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4120 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4124 * This table counts from float 0 to 1 in increments of .01, which is
4128 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4129 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4130 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4131 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4132 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4133 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4134 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4135 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4136 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4137 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4138 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4139 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4140 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4141 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4142 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4143 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4144 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4152 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4153 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4154 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4155 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4156 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4157 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4158 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4159 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4160 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4161 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4162 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4163 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4164 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4165 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4166 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4167 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4168 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4175 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4176 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4177 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4178 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4179 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4180 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4181 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4182 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4183 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4184 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4185 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4186 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4187 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4188 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4189 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4190 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4191 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4192 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4193 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4194 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4195 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4196 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4197 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4198 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4199 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4200 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4201 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4205 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4206 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4207 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4208 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4209 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4210 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4211 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4212 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4213 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4214 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4215 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4216 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4217 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4218 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4219 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4220 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4221 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4225 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4226 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4227 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4228 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4229 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4230 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4231 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4232 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4233 0x41C00000
4239 int i = 0;
4241 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4248 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4266 return 0;
4279 return 0;
4294 return 0;
4310 uinfo->value.integer.min = 0;
4314 return 0;
4329 return 0;
4336 return 0;
4345 uinfo->value.integer.min = 0;
4349 return 0;
4364 return 0;
4374 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4375 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4384 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4388 knew.tlv.c = 0;
4389 knew.tlv.p = 0;
4409 return 0;
4412 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4422 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4428 if (err < 0)
4432 return 0;
4445 /* EQ defaults to 0dB. */
4487 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4488 if (err < 0)
4492 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4493 if (err < 0)
4497 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4498 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4499 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4500 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4501 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4502 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4503 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4504 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4507 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4508 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4512 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4513 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4514 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4520 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4521 if (err < 0)
4525 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4526 if (err < 0)
4530 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4531 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4532 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4533 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4534 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4535 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4536 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4537 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4540 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4541 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4542 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4545 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4546 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4554 return err < 0 ? err : 0;
4572 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4588 return 0;
4591 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4592 err = dspio_set_uint_param(codec, 0x96,
4594 if (err < 0)
4599 err = dspio_set_uint_param(codec, 0x96,
4601 if (err < 0)
4604 err = dspio_set_uint_param(codec, 0x96,
4606 if (err < 0)
4614 err = dspio_set_uint_param(codec, 0x96,
4616 if (err < 0)
4620 return 0;
4636 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4637 if (err < 0)
4643 err = dspio_set_uint_param(codec, 0x96,
4645 if (err < 0)
4649 return 0;
4664 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4682 return 0;
4689 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4690 AC_VERB_GET_GPIO_DATA, 0);
4697 snd_hda_codec_write(codec, codec->core.afg, 0,
4702 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4709 for (i = 0; i < out_info->scp_cmds_count; i++) {
4714 if (err < 0)
4719 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4731 zxr_headphone_gain_set(codec, 0);
4742 return 0;
4750 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4751 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4801 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4802 if (err < 0)
4805 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4813 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4814 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4817 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4819 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4821 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4823 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4835 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4836 if (err < 0)
4842 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4843 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4846 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4847 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4848 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4859 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4861 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4863 if (err < 0)
4876 /* Set speaker EQ bypass attenuation to 0. */
4877 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4878 if (err < 0)
4885 err = dspio_set_uint_param(codec, 0x96,
4887 if (err < 0)
4894 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4897 err = dspio_set_uint_param(codec, 0x96,
4899 if (err < 0)
4904 if (err < 0)
4911 return err < 0 ? err : 0;
4927 jack->block_report = 0;
4948 return 0;
4950 /* if CrystalVoice if off, vipsource should be 0 */
4952 (val == 0)) {
4953 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4960 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4962 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4970 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4972 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4986 return 0;
4990 chipio_set_stream_control(codec, 0x03, 0);
4991 chipio_set_stream_control(codec, 0x04, 0);
4993 /* if CrystalVoice is off, vipsource should be 0 */
4995 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4997 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
5000 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5005 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5017 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5024 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5030 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5033 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5039 chipio_set_stream_control(codec, 0x03, 1);
5040 chipio_set_stream_control(codec, 0x04, 1);
5078 ca0132_mic_boost_set(codec, 0);
5086 ca0132_set_dmic(codec, 0);
5089 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5094 return 0;
5112 chipio_set_stream_control(codec, 0x03, 0);
5113 chipio_set_stream_control(codec, 0x04, 0);
5122 ca0113_mmio_gpio_set(codec, 0, false);
5133 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5137 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5143 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5153 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5155 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5157 chipio_set_stream_control(codec, 0x03, 1);
5158 chipio_set_stream_control(codec, 0x04, 1);
5161 chipio_write(codec, 0x18B098, 0x0000000C);
5162 chipio_write(codec, 0x18B09C, 0x0000000C);
5165 chipio_write(codec, 0x18B098, 0x0000000C);
5166 chipio_write(codec, 0x18B09C, 0x000000CC);
5169 chipio_write(codec, 0x18B098, 0x0000000C);
5170 chipio_write(codec, 0x18B09C, 0x0000004C);
5178 ca0132_mic_boost_set(codec, 0);
5182 ca0113_mmio_gpio_set(codec, 0, false);
5188 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5191 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5196 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5205 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5211 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5216 chipio_write(codec, 0x18B098, 0x00000000);
5217 chipio_write(codec, 0x18B09C, 0x00000000);
5222 chipio_set_stream_control(codec, 0x03, 1);
5223 chipio_set_stream_control(codec, 0x04, 1);
5229 ca0113_mmio_gpio_set(codec, 0, true);
5238 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5249 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5251 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5253 chipio_set_stream_control(codec, 0x03, 1);
5254 chipio_set_stream_control(codec, 0x04, 1);
5258 chipio_write(codec, 0x18B098, 0x0000000C);
5259 chipio_write(codec, 0x18B09C, 0x000000CC);
5262 chipio_write(codec, 0x18B098, 0x0000000C);
5263 chipio_write(codec, 0x18B09C, 0x0000004C);
5274 return 0;
5306 * They return 0 if no changed. Return 1 if changed.
5322 ca0132_voicefx.reqs[0], tmp);
5335 int err = 0;
5338 if ((idx < 0) || (idx >= num_fx))
5339 return 0; /* no changed */
5345 val = 0;
5350 val = 0;
5358 val = 0;
5362 val = 0;
5377 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5382 * to module ID 0x47. No clue why.
5396 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5402 val = 0;
5405 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5408 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5410 ca0132_effects[idx].reqs[0], on);
5412 if (err < 0)
5413 return 0; /* no changed */
5425 int i, ret = 0;
5446 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5447 AC_VERB_GET_CONV, 0);
5448 if (oldval != 0)
5449 snd_hda_codec_write(codec, spec->adcs[0], 0,
5451 0);
5460 if (oldval != 0)
5461 snd_hda_codec_write(codec, spec->adcs[0], 0,
5473 int i, ret = 0;
5486 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5501 int ret = 0;
5504 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5505 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5507 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5508 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5516 int ret = 0;
5518 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5519 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5527 for (i = 0; i < 4; i++)
5528 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5530 return 0;
5541 return 0;
5549 hda_nid_t shared_nid = 0;
5551 int ret = 0;
5598 0, dir);
5613 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5631 int i = 0;
5644 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5648 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5653 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5657 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5664 return 0;
5680 return 0;
5693 return 0;
5709 return 0;
5719 uinfo->value.integer.min = 0;
5723 return 0;
5743 return 0;
5753 return 0;
5768 return 0;
5775 return 0;
5782 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5800 return 0;
5809 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5810 return 0;
5818 int sel = ucontrol->value.enumerated.item[0];
5822 return 0;
5854 return 0;
5863 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5864 return 0;
5872 int sel = ucontrol->value.enumerated.item[0];
5876 return 0;
5907 return 0;
5916 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5917 return 0;
5925 int sel = ucontrol->value.enumerated.item[0];
5929 return 0;
5936 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5957 return 0;
5966 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5967 return 0;
5975 int sel = ucontrol->value.enumerated.item[0];
5986 return 0;
6009 return 0;
6018 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6019 return 0;
6027 int sel = ucontrol->value.enumerated.item[0];
6032 return 0;
6060 return 0;
6069 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6070 return 0;
6078 int sel = ucontrol->value.enumerated.item[0];
6082 return 0;
6113 return 0;
6122 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6123 return 0;
6131 int sel = ucontrol->value.enumerated.item[0];
6137 return 0;
6145 case 0:
6177 return 0;
6186 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6187 return 0;
6195 int i, err = 0;
6196 int sel = ucontrol->value.enumerated.item[0];
6200 return 0;
6205 * Idx 0 is default.
6208 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6212 if (err < 0)
6216 if (err >= 0)
6234 return 0;
6243 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6244 return 0;
6252 int i, err = 0;
6253 int sel = ucontrol->value.enumerated.item[0];
6256 return 0;
6262 * Idx 0 is default.
6265 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6269 if (err < 0)
6273 if (err >= 0) {
6276 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6301 return 0;
6307 return 0;
6311 if (nid == spec->input_pins[0]) {
6313 return 0;
6318 return 0;
6323 return 0;
6328 return 0;
6331 return 0;
6344 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6385 if (nid == spec->input_pins[0]) {
6404 changed = 0;
6414 changed = 0;
6422 changed = 0;
6453 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6485 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6495 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6524 return 0;
6535 hda_nid_t shared_nid = 0;
6559 0, dir);
6582 hda_nid_t vnid = 0;
6586 case 0x02:
6589 case 0x07:
6631 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6641 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6659 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6676 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6711 VOICEFX, 1, 0, HDA_INPUT);
6723 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6740 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6757 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6774 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6817 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6849 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6858 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6865 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6883 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6900 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6928 * I think this has to do with the pin for rear surround being 0x11,
6929 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6947 int err = 0;
6960 elem, hinfo->channels_max, 0, &chmap);
6961 if (err < 0)
6976 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6977 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6978 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6979 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6981 0x12, 1, HDA_INPUT),
6999 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7001 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7002 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7003 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7004 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7005 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7006 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7007 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
7009 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7010 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7021 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7023 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7024 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7025 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7026 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7027 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7028 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7031 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7032 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7042 int err = 0;
7045 for (i = 0; i < spec->num_mixers; i++) {
7047 if (err < 0)
7052 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7056 "Playback Volume", 0);
7060 true, 0, &spec->vmaster_mute.sw_kctl);
7061 if (err < 0)
7069 for (i = 0; i < num_fx; i++) {
7080 if (err < 0)
7090 if (err < 0)
7094 if (err < 0)
7098 "Enable OutFX", 0);
7099 if (err < 0)
7104 if (err < 0)
7108 for (i = 0; i < num_sliders; i++) {
7113 if (err < 0)
7120 if (err < 0)
7124 "PlayEnhancement", 0);
7125 if (err < 0)
7130 if (err < 0)
7134 if (err < 0)
7144 if (err < 0)
7147 if (err < 0)
7150 if (err < 0)
7153 if (err < 0)
7156 if (err < 0)
7159 if (err < 0)
7162 if (err < 0)
7170 if (err < 0)
7179 if (err < 0)
7182 if (err < 0)
7187 if (err < 0)
7199 if (err < 0)
7205 if (err < 0)
7208 if (err < 0)
7215 if (err < 0)
7222 return 0;
7228 int err = 0;
7233 if (err < 0)
7239 if (err < 0)
7243 return 0;
7303 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7308 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7329 return 0;
7346 return 0;
7359 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7363 return 0;
7380 return 0;
7388 snd_hda_codec_write(codec, pin, 0,
7393 snd_hda_codec_write(codec, dac, 0,
7402 snd_hda_codec_write(codec, pin, 0,
7404 AMP_IN_UNMUTE(0));
7407 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7408 AMP_IN_UNMUTE(0));
7410 /* init to 0 dB and unmute. */
7411 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7412 HDA_AMP_VOLMASK, 0x5a);
7413 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7414 HDA_AMP_MUTE, 0);
7440 ca0132_set_vipsource(codec, 0);
7444 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7447 val |= 0x80;
7448 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7451 if (!(spec->dmic_ctl & 0x20))
7456 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7460 val &= 0x5f;
7461 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7464 if (!(spec->dmic_ctl & 0x20))
7465 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7484 * Bit 2-0: MPIO select
7488 val = 0x01;
7489 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7493 * Bit 2-0: Data1 MPIO select
7498 val = 0x83;
7499 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7502 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7503 * Bit 3-0: Channel mask
7510 val = 0x33;
7512 val = 0x23;
7515 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7528 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7529 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7542 for (i = 0; i < spec->multiout.num_dacs; i++)
7545 for (i = 0; i < spec->num_outputs; i++)
7548 for (i = 0; i < spec->num_inputs; i++) {
7563 if (status >= 0) {
7564 /* AND against 0xfff to get the active channel bits. */
7565 tmp = tmp & 0xfff;
7580 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7583 if (status < 0)
7608 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7609 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7613 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7623 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7628 dsp_dma_stream_ids[i], 0);
7643 /* Make sure stream 0x0c is six channels. */
7644 chipio_set_stream_channels(codec, 0x0c, 6);
7646 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7658 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7661 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7664 * 0x0001f8c0
7668 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7669 * entry within the 0x190000 range, and when a range of entries is in use, the
7670 * ending value is overwritten with 0xff.
7671 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7672 * streamID's, where each entry is a starting 0x190000 port offset.
7673 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7681 * 0x00-0x1f: HDA audio stream input/output ports.
7682 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7683 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7684 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7685 * 0xe0-0xff: DAC/ADC audio input/output ports.
7688 * 0x03: Mic1 ADC to DSP.
7689 * 0x04: Mic2 ADC to DSP.
7690 * 0x05: HDA node 0x02 audio stream to DSP.
7691 * 0x0f: DSP Mic exit to HDA node 0x07.
7692 * 0x0c: DSP processed audio to DACs.
7693 * 0x14: DAC0, front L/R.
7707 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7711 * Check if the stream's port value is 0xff, because the 8051 may not
7715 if (stream_offset == 0xff) {
7716 for (i = 0; i < 5; i++) {
7719 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7722 if (stream_offset != 0xff)
7727 if (stream_offset == 0xff) {
7728 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7734 stream_offset *= 0x04;
7735 stream_offset += 0x190000;
7737 for (i = 0; i < remap_data->count; i++) {
7744 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7752 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7757 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7762 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7791 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7796 dspio_set_uint_param(codec, 0x96, i, tmp);
7801 dspio_set_uint_param(codec, 0x96, i, tmp);
7804 for (i = 0; i < 6; i++)
7805 dspio_set_uint_param(codec, 0x96,
7821 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7825 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7831 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7833 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7837 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7838 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7850 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7851 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7853 /* Setup stream 0x14 with it's source and destination points */
7854 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7855 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7856 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7857 chipio_set_stream_channels(codec, 0x14, 2);
7858 chipio_set_stream_control(codec, 0x14, 1);
7880 chipio_remap_stream(codec, &stream_remap_data[0]);
7909 chipio_set_stream_control(codec, 0x03, 0);
7910 chipio_set_stream_control(codec, 0x04, 0);
7916 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7918 chipio_set_stream_control(codec, 0x03, 1);
7919 chipio_set_stream_control(codec, 0x04, 1);
7923 chipio_write(codec, 0x18b098, 0x0000000c);
7924 chipio_write(codec, 0x18b09C, 0x0000000c);
7927 chipio_write(codec, 0x18b098, 0x0000000c);
7928 chipio_write(codec, 0x18b09c, 0x0000004c);
7939 chipio_8051_write_direct(codec, 0x93, 0x10);
7940 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7942 writeb(0xff, spec->mem_base + 0x304);
7943 writeb(0xff, spec->mem_base + 0x304);
7944 writeb(0xff, spec->mem_base + 0x304);
7945 writeb(0xff, spec->mem_base + 0x304);
7946 writeb(0x00, spec->mem_base + 0x100);
7947 writeb(0xff, spec->mem_base + 0x304);
7948 writeb(0x00, spec->mem_base + 0x100);
7949 writeb(0xff, spec->mem_base + 0x304);
7950 writeb(0x00, spec->mem_base + 0x100);
7951 writeb(0xff, spec->mem_base + 0x304);
7952 writeb(0x00, spec->mem_base + 0x100);
7953 writeb(0xff, spec->mem_base + 0x304);
7955 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7956 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7957 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7967 chipio_set_control_param(codec, 3, 0);
7974 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7975 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7977 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7982 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7983 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7984 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7985 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7986 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7995 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7997 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7999 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
8001 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
8002 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8003 chipio_set_stream_channels(codec, 0x18, 6);
8004 chipio_set_stream_control(codec, 0x18, 1);
8008 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8010 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
8021 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8022 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8023 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8024 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8026 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8028 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8029 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8030 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8031 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8032 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8033 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8034 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8035 ca0113_mmio_gpio_set(codec, 0, true);
8037 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8039 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8041 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8042 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8056 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8057 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8058 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8059 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8060 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8061 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8062 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8063 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8074 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8075 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8077 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8079 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8080 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8082 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8083 chipio_set_stream_channels(codec, 0x18, 6);
8084 chipio_set_stream_control(codec, 0x18, 1);
8094 0x41, 0x45, 0x40, 0x43, 0x51
8097 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8101 for (i = 0; i < ARRAY_SIZE(addr); i++)
8109 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8112 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8118 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8120 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8121 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8122 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8123 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8128 for (i = 0; i < ARRAY_SIZE(target); i++)
8129 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8131 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8132 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8133 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8135 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8136 chipio_set_stream_channels(codec, 0x21, 2);
8137 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8139 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8145 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8147 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8151 * seemingly sends data to the HDA node 0x09, which is the digital
8158 ca0113_mmio_gpio_set(codec, 0, 1);
8161 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8162 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8163 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8164 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8166 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8167 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8169 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8170 chipio_set_stream_channels(codec, 0x18, 6);
8189 chipio_8051_write_direct(codec, 0x93, 0x10);
8191 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8193 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8194 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8199 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8200 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8201 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8203 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8208 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8228 for (idx = 0; idx < num_fx; idx++) {
8229 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8238 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8241 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8245 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8246 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8250 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8254 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8276 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8280 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8284 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8297 for (idx = 0; idx < num_fx; idx++) {
8298 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8331 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8332 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8336 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8340 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8344 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8350 for (idx = 0; idx < num_fx; idx++) {
8351 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8380 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8381 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8382 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8383 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8385 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8386 ca0113_mmio_gpio_set(codec, 0, false);
8387 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8391 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8392 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8396 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8400 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8404 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8415 for (idx = 0; idx < num_fx; idx++) {
8416 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8445 dspio_set_uint_param(codec, 0x96,
8447 dspio_set_uint_param(codec, 0x96,
8450 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8453 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8454 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8456 ca0113_mmio_gpio_set(codec, 0, false);
8460 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8461 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8465 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8469 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8473 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8474 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8485 * Not sure why, but these are both set to 1. They're only set to 0
8488 ca0113_mmio_gpio_set(codec, 0, true);
8492 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8493 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8494 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8498 for (idx = 0; idx < num_fx; idx++) {
8499 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8523 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8524 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8526 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8530 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8532 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8534 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8536 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8538 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8552 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8553 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8554 chipio_set_control_param(codec, 0, 0);
8555 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8592 codec->card->dev) != 0)
8599 codec->card->dev) != 0)
8614 codec->card->dev) != 0)
8619 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8666 if (dspio_get_response_data(codec) >= 0)
8667 spec->wait_scp = 0;
8719 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8726 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8728 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8736 {0x15, 0x70D, 0xF0},
8737 {0x15, 0x70E, 0xFE},
8738 {0x15, 0x707, 0x75},
8739 {0x15, 0x707, 0xD3},
8740 {0x15, 0x707, 0x09},
8741 {0x15, 0x707, 0x53},
8742 {0x15, 0x707, 0xD4},
8743 {0x15, 0x707, 0xEF},
8744 {0x15, 0x707, 0x75},
8745 {0x15, 0x707, 0xD3},
8746 {0x15, 0x707, 0x09},
8747 {0x15, 0x707, 0x02},
8748 {0x15, 0x707, 0x37},
8749 {0x15, 0x707, 0x78},
8750 {0x15, 0x53C, 0xCE},
8751 {0x15, 0x575, 0xC9},
8752 {0x15, 0x53D, 0xCE},
8753 {0x15, 0x5B7, 0xC9},
8754 {0x15, 0x70D, 0xE8},
8755 {0x15, 0x70E, 0xFE},
8756 {0x15, 0x707, 0x02},
8757 {0x15, 0x707, 0x68},
8758 {0x15, 0x707, 0x62},
8759 {0x15, 0x53A, 0xCE},
8760 {0x15, 0x546, 0xC9},
8761 {0x15, 0x53B, 0xCE},
8762 {0x15, 0x5E8, 0xC9},
8768 {0x15, 0x70D, 0x20},
8769 {0x15, 0x70E, 0x19},
8770 {0x15, 0x707, 0x00},
8771 {0x15, 0x539, 0xCE},
8772 {0x15, 0x546, 0xC9},
8773 {0x15, 0x70D, 0xB7},
8774 {0x15, 0x70E, 0x09},
8775 {0x15, 0x707, 0x10},
8776 {0x15, 0x70D, 0xAF},
8777 {0x15, 0x70E, 0x09},
8778 {0x15, 0x707, 0x01},
8779 {0x15, 0x707, 0x05},
8780 {0x15, 0x70D, 0x73},
8781 {0x15, 0x70E, 0x09},
8782 {0x15, 0x707, 0x14},
8783 {0x15, 0x6FF, 0xC4},
8803 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8804 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8806 snd_hda_codec_write(codec, codec->core.afg, 0,
8807 AC_VERB_SET_CODEC_RESET, 0);
8808 snd_hda_codec_write(codec, codec->core.afg, 0,
8809 AC_VERB_SET_CODEC_RESET, 0);
8818 spec->cur_mic_boost = 0;
8820 for (i = 0; i < VNODES_COUNT; i++) {
8821 spec->vnode_lvol[i] = 0x5a;
8822 spec->vnode_rvol[i] = 0x5a;
8823 spec->vnode_lswitch[i] = 0;
8824 spec->vnode_rswitch[i] = 0;
8831 for (i = 0; i < num_fx; i++) {
8832 on = (unsigned int)ca0132_effects[i].reqs[0];
8833 spec->effects_switch[i] = on ? 1 : 0;
8841 spec->speaker_range_val[0] = 1;
8845 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8851 spec->voicefx_val = 0;
8853 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8874 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8885 for (i = 0; i < 4; i++)
8886 writeb(0x0, spec->mem_base + 0x100);
8887 for (i = 0; i < 8; i++)
8888 writeb(0xb3, spec->mem_base + 0x304);
8890 ca0113_mmio_gpio_set(codec, 0, false);
8899 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8902 snd_hda_codec_write(codec, 0x11, 0,
8903 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8905 for (i = 0; i < ARRAY_SIZE(pins); i++)
8906 snd_hda_codec_write(codec, pins[i], 0,
8907 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8912 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8915 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8916 snd_hda_codec_write(codec, pins[i], 0,
8917 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8925 if (dir >= 0)
8926 snd_hda_codec_write(codec, 0x01, 0,
8928 if (mask >= 0)
8929 snd_hda_codec_write(codec, 0x01, 0,
8932 if (data >= 0)
8933 snd_hda_codec_write(codec, 0x01, 0,
8939 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8942 for (i = 0; i < ARRAY_SIZE(pins); i++)
8943 snd_hda_codec_write(codec, pins[i], 0,
8944 AC_VERB_SET_POWER_STATE, 0x03);
8949 chipio_set_stream_control(codec, 0x03, 0);
8950 chipio_set_stream_control(codec, 0x04, 0);
8953 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8957 chipio_set_stream_control(codec, 0x14, 0);
8958 chipio_set_stream_control(codec, 0x0C, 0);
8960 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8961 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8963 chipio_write(codec, 0x18a020, 0x00000083);
8965 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8966 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8967 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8969 chipio_set_stream_control(codec, 0x0C, 0);
8971 chipio_set_control_param(codec, 0x0D, 0x24);
8976 snd_hda_codec_write(codec, 0x0B, 0,
8977 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8985 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8986 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8991 chipio_set_stream_control(codec, 0x03, 0);
8992 chipio_set_stream_control(codec, 0x04, 0);
8994 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8995 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8996 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8997 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8998 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8999 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
9000 ca0113_mmio_gpio_set(codec, 0, false);
9003 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9004 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9006 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9008 chipio_set_stream_control(codec, 0x18, 0);
9009 chipio_set_stream_control(codec, 0x0c, 0);
9011 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
9016 chipio_set_stream_control(codec, 0x18, 0);
9017 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9018 chipio_set_stream_channels(codec, 0x21, 0);
9019 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9020 chipio_set_control_param(codec, 0x20, 0x01);
9022 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9024 chipio_set_stream_control(codec, 0x18, 0);
9025 chipio_set_stream_control(codec, 0x0c, 0);
9027 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9028 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9029 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9030 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9031 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9032 ca0113_mmio_gpio_set(codec, 0, false);
9034 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9036 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9037 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9042 chipio_set_stream_control(codec, 0x03, 0);
9043 chipio_set_stream_control(codec, 0x04, 0);
9044 chipio_set_stream_control(codec, 0x14, 0);
9045 chipio_set_stream_control(codec, 0x0C, 0);
9047 chipio_set_conn_rate(codec, 0x41, SR_192_000);
9048 chipio_set_conn_rate(codec, 0x91, SR_192_000);
9050 chipio_write(codec, 0x18a020, 0x00000083);
9052 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9053 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9057 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9062 ca0113_mmio_gpio_set(codec, 0, false);
9064 ca0113_mmio_gpio_set(codec, 0, true);
9090 unsigned int cur_address = 0x390;
9092 unsigned int failure = 0;
9100 for (i = 0; i < 4; i++) {
9102 cur_address += 0x4;
9104 for (i = 0; i < 4; i++) {
9105 if (dsp_data_check[i] == 0xa1a2a3a4)
9117 while (failure && (reload != 0)) {
9122 failure = 0;
9123 for (i = 0; i < 4; i++) {
9125 cur_address += 0x4;
9127 for (i = 0; i < 4; i++) {
9128 if (dsp_data_check[i] == 0xa1a2a3a4)
9144 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9149 * to 0 just incase a value has lingered from a boot into Windows.
9153 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9154 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9155 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9156 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9157 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9158 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9159 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9160 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9170 writel(0x00820680, spec->mem_base + 0x01C);
9171 writel(0x00820680, spec->mem_base + 0x01C);
9173 chipio_write(codec, 0x18b0a4, 0x000000c2);
9175 snd_hda_codec_write(codec, 0x11, 0,
9176 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9181 chipio_write(codec, 0x18b0a4, 0x000000c2);
9183 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9185 snd_hda_codec_write(codec, 0x11, 0,
9186 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9191 chipio_write(codec, 0x18b0a4, 0x000000c2);
9193 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9194 chipio_8051_write_exram(codec, 0x1920, 0x00);
9195 chipio_8051_write_exram(codec, 0x1921, 0x40);
9197 snd_hda_codec_write(codec, 0x11, 0,
9198 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9208 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9209 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9212 chipio_write(codec, 0x189000, 0x0001f100);
9214 chipio_write(codec, 0x18900c, 0x0001f100);
9219 * 0xfa92 in exram. This function seems to have something to do with
9223 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9225 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9227 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9230 chipio_write(codec, 0x18902c, 0x00000000);
9232 chipio_write(codec, 0x18902c, 0x00000003);
9235 for (i = 0; i < ARRAY_SIZE(addr); i++)
9245 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9246 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9250 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9251 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9252 0x000000c1, 0x00000080
9256 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9257 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9258 0x000000c1, 0x00000080
9262 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9263 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9264 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9265 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9269 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9270 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9271 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9272 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9273 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9274 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9275 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9276 0x00000080, 0x00880680
9286 for (i = 0; i < 3; i++)
9287 writel(0x00000000, spec->mem_base + addr[i]);
9292 tmp[0] = 0x00880480;
9293 tmp[1] = 0x00000080;
9296 tmp[0] = 0x00820680;
9297 tmp[1] = 0x00000083;
9300 tmp[0] = 0x00880680;
9301 tmp[1] = 0x00000083;
9304 tmp[0] = 0x00000000;
9305 tmp[1] = 0x00000000;
9309 for (i = 0; i < 2; i++)
9325 for (i = 0; i < count; i++)
9340 writel(0x00000680, spec->mem_base + 0x1c);
9341 writel(0x00880680, spec->mem_base + 0x1c);
9344 for (i = 0; i < count; i++) {
9347 * a different value to 0x20c.
9350 writel(0x00800001, spec->mem_base + addr[i]);
9358 writel(0x00880680, spec->mem_base + 0x1c);
9380 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9381 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9385 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9386 0x01, 0x6b, 0x57
9391 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9404 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9406 chipio_8051_write_direct(codec, 0x93, 0x10);
9407 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9410 tmp[0] = 0x03;
9411 tmp[1] = 0x03;
9412 tmp[2] = 0x07;
9414 tmp[0] = 0x0f;
9415 tmp[1] = 0x0f;
9416 tmp[2] = 0x0f;
9419 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9426 for (i = 0; cur_addr < 12; i++, cur_addr++)
9432 writel(0x00800001, spec->mem_base + 0x20c);
9435 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9436 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9438 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9441 chipio_8051_write_direct(codec, 0x90, 0x00);
9442 chipio_8051_write_direct(codec, 0x90, 0x10);
9445 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9483 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9484 chipio_write(codec, 0x18b030, 0x00000020);
9487 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9491 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9494 chipio_write(codec, 0x18b008, 0x000000f8);
9495 chipio_write(codec, 0x18b008, 0x000000f0);
9496 chipio_write(codec, 0x18b030, 0x00000020);
9497 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9500 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9535 return 0;
9585 for (i = 0; i < spec->num_outputs; i++)
9586 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9588 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9590 for (i = 0; i < spec->num_inputs; i++)
9597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9598 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9600 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9628 return 0;
9637 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9640 for (i = 0; i < spec->num_inputs; i++)
9643 return 0;
9702 return 0;
9725 spec->dacs[0] = 0x2;
9726 spec->dacs[1] = 0x3;
9727 spec->dacs[2] = 0x4;
9773 spec->out_pins[0] = 0x0b; /* speaker out */
9774 spec->out_pins[1] = 0x0f;
9775 spec->shared_out_nid = 0x2;
9776 spec->unsol_tag_hp = 0x0f;
9778 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9779 spec->adcs[1] = 0x8; /* analog mic2 */
9780 spec->adcs[2] = 0xa; /* what u hear */
9783 spec->input_pins[0] = 0x12;
9784 spec->input_pins[1] = 0x11;
9785 spec->input_pins[2] = 0x13;
9786 spec->shared_mic_nid = 0x7;
9787 spec->unsol_tag_amic1 = 0x11;
9792 spec->out_pins[0] = 0x0B; /* Line out */
9793 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9794 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9795 spec->out_pins[3] = 0x11; /* Rear surround */
9796 spec->shared_out_nid = 0x2;
9800 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9801 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9802 spec->adcs[2] = 0xa; /* what u hear */
9805 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9806 spec->input_pins[1] = 0x13; /* What U Hear */
9807 spec->shared_mic_nid = 0x7;
9808 spec->unsol_tag_amic1 = spec->input_pins[0];
9811 spec->dig_out = 0x05;
9813 spec->dig_in = 0x09;
9817 spec->out_pins[0] = 0x0B; /* Line out */
9818 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9819 spec->out_pins[2] = 0x10; /* Center/LFE */
9820 spec->out_pins[3] = 0x11; /* Rear surround */
9821 spec->shared_out_nid = 0x2;
9825 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9826 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9827 spec->adcs[2] = 0xa; /* what u hear */
9830 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9831 spec->input_pins[1] = 0x13; /* What U Hear */
9832 spec->shared_mic_nid = 0x7;
9833 spec->unsol_tag_amic1 = spec->input_pins[0];
9836 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9839 spec->input_pins[0] = 0x11; /* RCA Line-in */
9841 spec->dig_out = 0x05;
9844 spec->dig_in = 0x09;
9849 spec->out_pins[0] = 0x0B; /* Line out */
9850 spec->out_pins[1] = 0x11; /* Rear headphone out */
9851 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9852 spec->out_pins[3] = 0x0F; /* Rear surround */
9853 spec->shared_out_nid = 0x2;
9857 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9858 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9859 spec->adcs[2] = 0xa; /* what u hear */
9862 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9863 spec->input_pins[1] = 0x13; /* What U Hear */
9864 spec->shared_mic_nid = 0x7;
9865 spec->unsol_tag_amic1 = spec->input_pins[0];
9868 spec->dig_out = 0x05;
9873 spec->out_pins[0] = 0x0B; /* Line out */
9874 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9875 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9876 spec->out_pins[3] = 0x11; /* Rear surround */
9877 spec->shared_out_nid = 0x2;
9881 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9882 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9883 spec->adcs[2] = 0x0a; /* what u hear */
9886 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9887 spec->input_pins[1] = 0x13; /* What U Hear */
9888 spec->shared_mic_nid = 0x7;
9889 spec->unsol_tag_amic1 = spec->input_pins[0];
9892 spec->dig_out = 0x05;
9897 spec->out_pins[0] = 0x0b; /* speaker out */
9898 spec->out_pins[1] = 0x10; /* headphone out */
9899 spec->shared_out_nid = 0x2;
9902 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9903 spec->adcs[1] = 0x8; /* analog mic2 */
9904 spec->adcs[2] = 0xa; /* what u hear */
9907 spec->input_pins[0] = 0x12;
9908 spec->input_pins[1] = 0x11;
9909 spec->input_pins[2] = 0x13;
9910 spec->shared_mic_nid = 0x7;
9911 spec->unsol_tag_amic1 = spec->input_pins[0];
9914 spec->dig_out = 0x05;
9916 spec->dig_in = 0x09;
9941 spec->spec_init_verbs[0].nid = 0x0b;
9942 spec->spec_init_verbs[0].param = 0x78D;
9943 spec->spec_init_verbs[0].verb = 0x00;
9947 spec->spec_init_verbs[2].nid = 0x0b;
9949 spec->spec_init_verbs[2].verb = 0x02;
9951 spec->spec_init_verbs[3].nid = 0x10;
9952 spec->spec_init_verbs[3].param = 0x78D;
9953 spec->spec_init_verbs[3].verb = 0x02;
9955 spec->spec_init_verbs[4].nid = 0x10;
9957 spec->spec_init_verbs[4].verb = 0x02;
9961 return 0;
9973 case 0x11020033:
9976 case 0x1102003f:
10018 spec->mixers[0] = desktop_mixer;
10022 spec->mixers[0] = desktop_mixer;
10028 spec->mixers[0] = desktop_mixer;
10032 spec->mixers[0] = r3di_mixer;
10036 spec->mixers[0] = desktop_mixer;
10040 spec->mixers[0] = desktop_mixer;
10044 spec->mixers[0] = ca0132_mixer;
10073 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10091 if (err < 0)
10095 if (err < 0)
10100 return 0;
10111 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),