12 #define DSP_CHIP_OFFSET                0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET      0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT         0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT         0x3
19 #define DSP_DBGCNTL_EXEC_MASK          0xF
21 #define DSP_DBGCNTL_SS_LOBIT           0x4
22 #define DSP_DBGCNTL_SS_HIBIT           0x7
23 #define DSP_DBGCNTL_SS_MASK            0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT        0xA
26 #define DSP_DBGCNTL_STATE_HIBIT        0xD
27 #define DSP_DBGCNTL_STATE_MASK         0x3C00
29 #define XRAM_CHIP_OFFSET               0x0
30 #define XRAM_XRAM_CHANNEL_COUNT        0xE000
31 #define XRAM_XRAM_MODULE_OFFSET        0x0
37 #define YRAM_CHIP_OFFSET               0x40000
38 #define YRAM_YRAM_CHANNEL_COUNT        0x8000
39 #define YRAM_YRAM_MODULE_OFFSET        0x0
45 #define UC_CHIP_OFFSET                 0x80000
46 #define UC_UC_CHANNEL_COUNT            0x10000
47 #define UC_UC_MODULE_OFFSET            0x0
53 #define AXRAM_CHIP_OFFSET              0x3C000
54 #define AXRAM_AXRAM_CHANNEL_COUNT      0x1000
55 #define AXRAM_AXRAM_MODULE_OFFSET      0x0
61 #define AYRAM_CHIP_OFFSET              0x78000
62 #define AYRAM_AYRAM_CHANNEL_COUNT      0x1000
63 #define AYRAM_AYRAM_MODULE_OFFSET      0x0
69 #define DSPDMAC_CHIP_OFFSET            0x110000
71 #define DSPDMAC_DMACFG_MODULE_OFFSET   0xF00
72 #define DSPDMAC_DMACFG_CHAN_INCR       0x10
77 #define DSPDMAC_DMACFG_DBADR_LOBIT     0x0
78 #define DSPDMAC_DMACFG_DBADR_HIBIT     0x10
79 #define DSPDMAC_DMACFG_DBADR_MASK      0x1FFFF
80 #define DSPDMAC_DMACFG_LP_LOBIT        0x11
81 #define DSPDMAC_DMACFG_LP_HIBIT        0x11
82 #define DSPDMAC_DMACFG_LP_MASK         0x20000
84 #define DSPDMAC_DMACFG_AINCR_LOBIT     0x12
85 #define DSPDMAC_DMACFG_AINCR_HIBIT     0x12
86 #define DSPDMAC_DMACFG_AINCR_MASK      0x40000
88 #define DSPDMAC_DMACFG_DWR_LOBIT       0x13
89 #define DSPDMAC_DMACFG_DWR_HIBIT       0x13
90 #define DSPDMAC_DMACFG_DWR_MASK        0x80000
92 #define DSPDMAC_DMACFG_AJUMP_LOBIT     0x14
93 #define DSPDMAC_DMACFG_AJUMP_HIBIT     0x17
94 #define DSPDMAC_DMACFG_AJUMP_MASK      0xF00000
96 #define DSPDMAC_DMACFG_AMODE_LOBIT     0x18
97 #define DSPDMAC_DMACFG_AMODE_HIBIT     0x19
98 #define DSPDMAC_DMACFG_AMODE_MASK      0x3000000
100 #define DSPDMAC_DMACFG_LK_LOBIT        0x1A
101 #define DSPDMAC_DMACFG_LK_HIBIT        0x1A
102 #define DSPDMAC_DMACFG_LK_MASK         0x4000000
104 #define DSPDMAC_DMACFG_AICS_LOBIT      0x1B
105 #define DSPDMAC_DMACFG_AICS_HIBIT      0x1F
106 #define DSPDMAC_DMACFG_AICS_MASK       0xF8000000
108 #define DSPDMAC_DMACFG_LP_SINGLE                 0
111 #define DSPDMAC_DMACFG_AINCR_XANDY               0
114 #define DSPDMAC_DMACFG_DWR_DMA_RD                0
117 #define DSPDMAC_DMACFG_AMODE_LINEAR              0
123 #define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04
124 #define DSPDMAC_DSPADROFS_CHAN_INCR    0x10
129 #define DSPDMAC_DSPADROFS_COFS_LOBIT   0x0
130 #define DSPDMAC_DSPADROFS_COFS_HIBIT   0xF
131 #define DSPDMAC_DSPADROFS_COFS_MASK    0xFFFF
133 #define DSPDMAC_DSPADROFS_BOFS_LOBIT   0x10
134 #define DSPDMAC_DSPADROFS_BOFS_HIBIT   0x1F
135 #define DSPDMAC_DSPADROFS_BOFS_MASK    0xFFFF0000
138 #define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04
139 #define DSPDMAC_DSPADRWOFS_CHAN_INCR   0x10
145 #define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0
146 #define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA
147 #define DSPDMAC_DSPADRWOFS_WCOFS_MASK  0x7FF
149 #define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB
150 #define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF
151 #define DSPDMAC_DSPADRWOFS_WCBFR_MASK  0xF800
153 #define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10
154 #define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A
155 #define DSPDMAC_DSPADRWOFS_WBOFS_MASK  0x7FF0000
157 #define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B
158 #define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F
159 #define DSPDMAC_DSPADRWOFS_WBBFR_MASK  0xF8000000
162 #define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04
163 #define DSPDMAC_DSPADRGOFS_CHAN_INCR   0x10
168 #define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0
169 #define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9
170 #define DSPDMAC_DSPADRGOFS_GCOFS_MASK  0x3FF
172 #define DSPDMAC_DSPADRGOFS_GCS_LOBIT   0xA
173 #define DSPDMAC_DSPADRGOFS_GCS_HIBIT   0xC
174 #define DSPDMAC_DSPADRGOFS_GCS_MASK    0x1C00
176 #define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD
177 #define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF
178 #define DSPDMAC_DSPADRGOFS_GCBFR_MASK  0xE000
180 #define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10
181 #define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19
182 #define DSPDMAC_DSPADRGOFS_GBOFS_MASK  0x3FF0000
184 #define DSPDMAC_DSPADRGOFS_GBS_LOBIT   0x1A
185 #define DSPDMAC_DSPADRGOFS_GBS_HIBIT   0x1C
186 #define DSPDMAC_DSPADRGOFS_GBS_MASK    0x1C000000
188 #define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D
189 #define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F
190 #define DSPDMAC_DSPADRGOFS_GBBFR_MASK  0xE0000000
193 #define DSPDMAC_XFRCNT_MODULE_OFFSET   0xF08
194 #define DSPDMAC_XFRCNT_CHAN_INCR       0x10
200 #define DSPDMAC_XFRCNT_CCNT_LOBIT      0x0
201 #define DSPDMAC_XFRCNT_CCNT_HIBIT      0xF
202 #define DSPDMAC_XFRCNT_CCNT_MASK       0xFFFF
204 #define DSPDMAC_XFRCNT_BCNT_LOBIT      0x10
205 #define DSPDMAC_XFRCNT_BCNT_HIBIT      0x1F
206 #define DSPDMAC_XFRCNT_BCNT_MASK       0xFFFF0000
209 #define DSPDMAC_IRQCNT_MODULE_OFFSET   0xF0C
210 #define DSPDMAC_IRQCNT_CHAN_INCR       0x10
215 #define DSPDMAC_IRQCNT_CICNT_LOBIT     0x0
216 #define DSPDMAC_IRQCNT_CICNT_HIBIT     0xF
217 #define DSPDMAC_IRQCNT_CICNT_MASK      0xFFFF
219 #define DSPDMAC_IRQCNT_BICNT_LOBIT     0x10
220 #define DSPDMAC_IRQCNT_BICNT_HIBIT     0x1F
221 #define DSPDMAC_IRQCNT_BICNT_MASK      0xFFFF0000
224 #define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0
225 #define DSPDMAC_AUDCHSEL_CHAN_INCR     0x4
230 #define DSPDMAC_AUDCHSEL_ACS_LOBIT     0x0
231 #define DSPDMAC_AUDCHSEL_ACS_HIBIT     0x1F
232 #define DSPDMAC_AUDCHSEL_ACS_MASK      0xFFFFFFFF
234 #define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0
238 #define DSPDMAC_CHNLSTART_EN_LOBIT     0x0
239 #define DSPDMAC_CHNLSTART_EN_HIBIT     0xB
240 #define DSPDMAC_CHNLSTART_EN_MASK      0xFFF
242 #define DSPDMAC_CHNLSTART_VAI1_LOBIT   0xC
243 #define DSPDMAC_CHNLSTART_VAI1_HIBIT   0xF
244 #define DSPDMAC_CHNLSTART_VAI1_MASK    0xF000
246 #define DSPDMAC_CHNLSTART_DIS_LOBIT    0x10
247 #define DSPDMAC_CHNLSTART_DIS_HIBIT    0x1B
248 #define DSPDMAC_CHNLSTART_DIS_MASK     0xFFF0000
250 #define DSPDMAC_CHNLSTART_VAI2_LOBIT   0x1C
251 #define DSPDMAC_CHNLSTART_VAI2_HIBIT   0x1F
252 #define DSPDMAC_CHNLSTART_VAI2_MASK    0xF0000000
254 #define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4
258 #define DSPDMAC_CHNLSTATUS_ISC_LOBIT   0x0
259 #define DSPDMAC_CHNLSTATUS_ISC_HIBIT   0xB
260 #define DSPDMAC_CHNLSTATUS_ISC_MASK    0xFFF
262 #define DSPDMAC_CHNLSTATUS_AOO_LOBIT   0xC
263 #define DSPDMAC_CHNLSTATUS_AOO_HIBIT   0xC
264 #define DSPDMAC_CHNLSTATUS_AOO_MASK    0x1000
266 #define DSPDMAC_CHNLSTATUS_AOU_LOBIT   0xD
267 #define DSPDMAC_CHNLSTATUS_AOU_HIBIT   0xD
268 #define DSPDMAC_CHNLSTATUS_AOU_MASK    0x2000
270 #define DSPDMAC_CHNLSTATUS_AIO_LOBIT   0xE
271 #define DSPDMAC_CHNLSTATUS_AIO_HIBIT   0xE
272 #define DSPDMAC_CHNLSTATUS_AIO_MASK    0x4000
274 #define DSPDMAC_CHNLSTATUS_AIU_LOBIT   0xF
275 #define DSPDMAC_CHNLSTATUS_AIU_HIBIT   0xF
276 #define DSPDMAC_CHNLSTATUS_AIU_MASK    0x8000
278 #define DSPDMAC_CHNLSTATUS_IEN_LOBIT   0x10
279 #define DSPDMAC_CHNLSTATUS_IEN_HIBIT   0x1B
280 #define DSPDMAC_CHNLSTATUS_IEN_MASK    0xFFF0000
282 #define DSPDMAC_CHNLSTATUS_VAI0_LOBIT  0x1C
283 #define DSPDMAC_CHNLSTATUS_VAI0_HIBIT  0x1F
284 #define DSPDMAC_CHNLSTATUS_VAI0_MASK   0xF0000000
286 #define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8
290 #define DSPDMAC_CHNLPROP_DCON_LOBIT    0x0
291 #define DSPDMAC_CHNLPROP_DCON_HIBIT    0xB
292 #define DSPDMAC_CHNLPROP_DCON_MASK     0xFFF
294 #define DSPDMAC_CHNLPROP_FFS_LOBIT     0xC
295 #define DSPDMAC_CHNLPROP_FFS_HIBIT     0xC
296 #define DSPDMAC_CHNLPROP_FFS_MASK      0x1000
298 #define DSPDMAC_CHNLPROP_NAJ_LOBIT     0xD
299 #define DSPDMAC_CHNLPROP_NAJ_HIBIT     0xD
300 #define DSPDMAC_CHNLPROP_NAJ_MASK      0x2000
302 #define DSPDMAC_CHNLPROP_ENH_LOBIT     0xE
303 #define DSPDMAC_CHNLPROP_ENH_HIBIT     0xE
304 #define DSPDMAC_CHNLPROP_ENH_MASK      0x4000
306 #define DSPDMAC_CHNLPROP_MSPCE_LOBIT   0x10
307 #define DSPDMAC_CHNLPROP_MSPCE_HIBIT   0x1B
308 #define DSPDMAC_CHNLPROP_MSPCE_MASK    0xFFF0000
310 #define DSPDMAC_CHNLPROP_AC_LOBIT      0x1C
311 #define DSPDMAC_CHNLPROP_AC_HIBIT      0x1F
312 #define DSPDMAC_CHNLPROP_AC_MASK       0xF0000000
314 #define DSPDMAC_ACTIVE_MODULE_OFFSET   0xFFC
318 #define DSPDMAC_ACTIVE_AAR_LOBIT       0x0
319 #define DSPDMAC_ACTIVE_AAR_HIBIT       0xB
320 #define DSPDMAC_ACTIVE_AAR_MASK        0xFFF
322 #define DSPDMAC_ACTIVE_WFR_LOBIT       0xC
323 #define DSPDMAC_ACTIVE_WFR_HIBIT       0x17
324 #define DSPDMAC_ACTIVE_WFR_MASK        0xFFF000
326 #define DSP_AUX_MEM_BASE            0xE000
327 #define INVALID_CHIP_ADDRESS        (~0U)
338 #define U64K 0x10000UL
350 #define X_RANGE_MAIN(a, s) \  argument
351 	(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR <  X_END))
352 #define X_RANGE_AUX(a, s)  \  argument
353 	(((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
354 #define X_RANGE_EXT(a, s)  \  argument
355 	(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR <  X_EXT))
356 #define X_RANGE_ALL(a, s)  \  argument
357 	(((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))
359 #define Y_RANGE_MAIN(a, s) \  argument
360 	(((a) >= YRAM_CHIP_OFFSET) && \
361 	((a)+((s)-1)*YRAM_YRAM_CHAN_INCR <  Y_END))
362 #define Y_RANGE_AUX(a, s)  \  argument
363 	(((a) >= Y_END) && \
364 	((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
365 #define Y_RANGE_EXT(a, s)  \  argument
366 	(((a) >= YRAM_CHIP_OFFSET) && \
367 	((a)+((s)-1)*YRAM_YRAM_CHAN_INCR <  Y_EXT))
368 #define Y_RANGE_ALL(a, s)  \  argument
369 	(((a) >= YRAM_CHIP_OFFSET) && \
370 	((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))
372 #define UC_RANGE(a, s) \  argument
373 	(((a) >= UC_CHIP_OFFSET) && \
374 	((a)+((s)-1)*UC_UC_CHAN_INCR     < UC_END))
376 #define X_OFF(a) \  argument
377 	(((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR)
378 #define AX_OFF(a) \  argument
379 	(((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \
382 #define Y_OFF(a) \  argument
383 	(((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR)
384 #define AY_OFF(a) \  argument
385 	(((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \
388 #define UC_OFF(a)  (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR)  argument
390 #define X_EXT_MAIN_SIZE(a)  (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a))  argument
391 #define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a))  argument
393 #define Y_EXT_MAIN_SIZE(a)  (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a))  argument
394 #define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a))  argument