Lines Matching +full:reg +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Lee Revell <rlrevell@joe-job.com>
5 * James Courtier-Dutton <James@superbug.co.uk>
19 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg)
23 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK)
26 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK))
31 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn)
36 regptr = (reg << 16) | chn;
40 scoped_guard(spinlock_irqsave, &emu->emu_lock) {
41 outl(regptr, emu->port + PTR);
42 val = inl(emu->port + DATA);
45 if (reg & 0xff000000) {
48 size = (reg >> 24) & 0x3f;
49 offset = (reg >> 16) & 0x1f;
50 mask = (1 << size) - 1;
60 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data)
65 regptr = (reg << 16) | chn;
69 guard(spinlock_irqsave)(&emu->emu_lock);
70 if (reg & 0xff000000) {
73 size = (reg >> 24) & 0x3f;
74 offset = (reg >> 16) & 0x1f;
75 mask = (1 << size) - 1;
76 if (snd_BUG_ON(data & ~mask))
79 data <<= offset;
81 outl(regptr, emu->port + PTR);
82 data |= inl(emu->port + DATA) & ~mask;
84 outl(regptr, emu->port + PTR);
86 outl(data, emu->port + DATA);
100 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16);
103 guard(spinlock_irqsave)(&emu->emu_lock);
105 u32 data;
106 u32 reg = va_arg(va, u32);
107 if (reg == REGLIST_END)
109 data = va_arg(va, u32);
110 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here
112 outl((reg << 16) | chn, emu->port + PTR);
113 outl(data, emu->port + DATA);
121 unsigned int reg,
126 regptr = (reg << 16) | chn;
128 guard(spinlock_irqsave)(&emu->emu_lock);
129 outl(regptr, emu->port + PTR2);
130 return inl(emu->port + DATA2);
134 unsigned int reg,
136 unsigned int data)
140 regptr = (reg << 16) | chn;
142 guard(spinlock_irqsave)(&emu->emu_lock);
143 outl(regptr, emu->port + PTR2);
144 outl(data, emu->port + DATA2);
148 unsigned int data)
151 unsigned int reg, tmp;
154 /* This function is not re-entrant, so protect against it. */
155 guard(spinlock)(&emu->spi_lock);
156 if (emu->card_capabilities->ca0108_chip)
157 reg = P17V_SPI;
163 if (data > 0xffff) {
168 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
171 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
172 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
173 snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
178 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
188 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
189 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
195 u32 reg,
203 if ((reg > 0x7f) || (value > 0x1ff)) {
204 dev_err(emu->card->dev, "i2c_write: invalid values.\n");
205 return -EINVAL;
208 /* This function is not re-entrant, so protect against it. */
209 guard(spinlock)(&emu->i2c_lock);
211 tmp = reg << 25 | value << 16;
218 /* Send the data to i2c */
232 dev_warn(emu->card->dev,
244 dev_err(emu->card->dev, "Writing to ADC failed!\n");
245 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n",
246 status, reg, value);
248 return -EINVAL;
254 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value)
256 if (snd_BUG_ON(reg > 0x3f))
258 reg += 0x40; /* 0x40 upwards are registers. */
261 outw(reg, emu->port + A_GPIO);
263 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
265 outw(value, emu->port + A_GPIO);
267 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
271 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
273 if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock)))
275 snd_emu1010_fpga_write_locked(emu, reg, value);
278 void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value)
281 snd_emu1010_fpga_write_locked(emu, reg, value);
284 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
290 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
292 if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock)))
294 if (snd_BUG_ON(reg > 0x3f))
296 reg += 0x40; /* 0x40 upwards are registers. */
297 outw(reg, emu->port + A_GPIO);
299 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
301 *value = ((inw(emu->port + A_GPIO) >> 8) & mask);
370 switch (emu->emu1010.wclock) {
381 emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK);
395 emu->emu1010.word_clock = clock;
409 // On E-MU 1010 rev1 the FPGA is a Xilinx Spartan IIE XC2S50E.
410 // On E-MU 0404b it is a Xilinx Spartan III XC3S50.
412 // GPO7 -> FPGA input & 1K resistor -> FPGA /PGMN <- FPGA output
416 // EMU_HANA_FPGA_CONFIG puts the FPGA output into high-Z mode, at
419 // GPO6 -> FPGA CCLK & FPGA input
420 // GPO5 -> FPGA DIN (dual function)
428 outw(0x00, emu->port + A_GPIO);
429 write_post = inw(emu->port + A_GPIO);
431 outw(0x80, emu->port + A_GPIO);
432 write_post = inw(emu->port + A_GPIO);
436 for (int n = 0; n < fw_entry->size; n++) {
437 u8 value = fw_entry->data[n];
439 u16 reg = 0x80;
441 reg |= 0x20;
443 outw(reg, emu->port + A_GPIO);
444 write_post = inw(emu->port + A_GPIO);
445 outw(reg | 0x40, emu->port + A_GPIO);
446 write_post = inw(emu->port + A_GPIO);
453 outw(0x10, emu->port + A_GPIO);
454 write_post = inw(emu->port + A_GPIO);
461 guard(spinlock_irqsave)(&emu->emu_lock);
462 enable = inl(emu->port + INTE) | intrenb;
463 outl(enable, emu->port + INTE);
470 guard(spinlock_irqsave)(&emu->emu_lock);
471 enable = inl(emu->port + INTE) & ~intrenb;
472 outl(enable, emu->port + INTE);
479 guard(spinlock_irqsave)(&emu->emu_lock);
481 outl(CLIEH << 16, emu->port + PTR);
482 val = inl(emu->port + DATA);
483 val |= 1 << (voicenum - 32);
485 outl(CLIEL << 16, emu->port + PTR);
486 val = inl(emu->port + DATA);
489 outl(val, emu->port + DATA);
496 guard(spinlock_irqsave)(&emu->emu_lock);
498 outl(CLIEH << 16, emu->port + PTR);
499 val = inl(emu->port + DATA);
500 val &= ~(1 << (voicenum - 32));
502 outl(CLIEL << 16, emu->port + PTR);
503 val = inl(emu->port + DATA);
506 outl(val, emu->port + DATA);
511 guard(spinlock_irqsave)(&emu->emu_lock);
513 outl(CLIPH << 16, emu->port + PTR);
514 voicenum = 1 << (voicenum - 32);
516 outl(CLIPL << 16, emu->port + PTR);
519 outl(voicenum, emu->port + DATA);
526 guard(spinlock_irqsave)(&emu->emu_lock);
528 outl(HLIEH << 16, emu->port + PTR);
529 val = inl(emu->port + DATA);
530 val |= 1 << (voicenum - 32);
532 outl(HLIEL << 16, emu->port + PTR);
533 val = inl(emu->port + DATA);
536 outl(val, emu->port + DATA);
543 guard(spinlock_irqsave)(&emu->emu_lock);
545 outl(HLIEH << 16, emu->port + PTR);
546 val = inl(emu->port + DATA);
547 val &= ~(1 << (voicenum - 32));
549 outl(HLIEL << 16, emu->port + PTR);
550 val = inl(emu->port + DATA);
553 outl(val, emu->port + DATA);
558 guard(spinlock_irqsave)(&emu->emu_lock);
560 outl(HLIPH << 16, emu->port + PTR);
561 voicenum = 1 << (voicenum - 32);
563 outl(HLIPL << 16, emu->port + PTR);
566 outl(voicenum, emu->port + DATA);
574 guard(spinlock_irqsave)(&emu->emu_lock);
576 outl(SOLEH << 16, emu->port + PTR);
577 sol = inl(emu->port + DATA);
578 sol |= 1 << (voicenum - 32);
580 outl(SOLEL << 16, emu->port + PTR);
581 sol = inl(emu->port + DATA);
584 outl(sol, emu->port + DATA);
591 guard(spinlock_irqsave)(&emu->emu_lock);
593 outl(SOLEH << 16, emu->port + PTR);
594 sol = inl(emu->port + DATA);
595 sol &= ~(1 << (voicenum - 32));
597 outl(SOLEL << 16, emu->port + PTR);
598 sol = inl(emu->port + DATA);
601 outl(sol, emu->port + DATA);
607 guard(spinlock_irqsave)(&emu->emu_lock);
608 outl(SOLEL << 16, emu->port + PTR);
609 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA);
610 outl(SOLEH << 16, emu->port + PTR);
611 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA);
616 guard(spinlock_irqsave)(&emu->emu_lock);
617 outl(SOLEL << 16, emu->port + PTR);
618 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA);
619 outl(SOLEH << 16, emu->port + PTR);
620 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA);
627 int ret = -EIO;
629 spin_lock_irqsave(&emu->emu_lock, flags);
631 outl(SOLEL << 16, emu->port + PTR);
632 soll = inl(emu->port + DATA);
633 outl(SOLEH << 16, emu->port + PTR);
634 solh = inl(emu->port + DATA);
640 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2);
642 u32 wc = inl(emu->port + WC);
646 outl(SOLEL << 16, emu->port + PTR);
647 outl(soll, emu->port + DATA);
650 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC));
660 outl(SOLEH << 16, emu->port + PTR);
661 outl(solh, emu->port + DATA);
663 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) ==
667 ret = -EAGAIN;
672 spin_unlock_irqrestore(&emu->emu_lock, flags);
674 spin_lock_irqsave(&emu->emu_lock, flags);
677 spin_unlock_irqrestore(&emu->emu_lock, flags);
686 curtime = inl(emu->port + WC) >> 6;
687 while (wait-- > 0) {
690 newtime = inl(emu->port + WC) >> 6;
700 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
702 struct snd_emu10k1 *emu = ac97->private_data;
704 guard(spinlock_irqsave)(&emu->emu_lock);
705 outb(reg, emu->port + AC97ADDRESS);
706 return inw(emu->port + AC97DATA);
709 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data)
711 struct snd_emu10k1 *emu = ac97->private_data;
713 guard(spinlock_irqsave)(&emu->emu_lock);
714 outb(reg, emu->port + AC97ADDRESS);
715 outw(data, emu->port + AC97DATA);