Lines Matching +full:clock +full:- +full:mode
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV;
49 dev_err(chip->card->dev,
50 "init_hw - could not initialize DSP comm page\n");
54 chip->device_id = device_id;
55 chip->subdevice_id = subdevice_id;
56 chip->bad_board = true;
57 chip->input_clock_types =
60 chip->digital_modes =
66 if (chip->device_id == DEVICE_ID_56361)
67 chip->dsp_code_to_load = FW_MONA_361_DSP;
69 chip->dsp_code_to_load = FW_MONA_301_DSP;
74 chip->bad_board = false;
83 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
84 chip->professional_spdif = false;
85 chip->digital_in_automute = true;
95 /* Map the DSP clock detect bits to the generic driver clock
97 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
123 if (chip->asic_loaded)
128 if (chip->device_id == DEVICE_ID_56361)
137 chip->asic_code = asic;
149 /* Set up the control register if the load succeeded -
150 48 kHz, internal clock, S/PDIF RCA mode */
161 /* Depending on what digital mode you want, Mona needs different ASICs
162 loaded. This function checks the ASIC needed for the new mode and sees
169 /* Check the clock detect bits to see if this is
170 a single-speed clock or a double-speed clock; load
172 if (chip->device_id == DEVICE_ID_56361) {
184 if (asic != chip->asic_code) {
190 chip->asic_code = asic;
200 u32 control_reg, clock;
204 /* Only set the clock for internal mode. */
205 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
206 dev_dbg(chip->card->dev,
207 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
209 chip->comm_page->sample_rate = cpu_to_le32(rate);
210 chip->sample_rate = rate;
216 if (chip->digital_mode == DIGITAL_MODE_ADAT)
217 return -EINVAL;
218 if (chip->device_id == DEVICE_ID_56361)
223 if (chip->device_id == DEVICE_ID_56361)
230 if (asic != chip->asic_code) {
233 spin_unlock_irq(&chip->lock);
236 spin_lock_irq(&chip->lock);
240 chip->asic_code = asic;
245 clock = 0;
246 control_reg = le32_to_cpu(chip->comm_page->control_register);
252 clock = GML_96KHZ;
255 clock = GML_88KHZ;
258 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
261 clock = GML_44KHZ;
262 /* Professional mode */
264 clock |= GML_SPDIF_SAMPLE_RATE0;
267 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
271 clock = GML_22KHZ;
274 clock = GML_16KHZ;
277 clock = GML_11KHZ;
280 clock = GML_8KHZ;
283 dev_err(chip->card->dev,
285 return -EINVAL;
288 control_reg |= clock;
290 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
291 chip->sample_rate = rate;
292 dev_dbg(chip->card->dev,
293 "set_sample_rate: %d clock %d\n", rate, clock);
300 static int set_input_clock(struct echoaudio *chip, u16 clock)
305 /* Mask off the clock select bits */
306 control_reg = le32_to_cpu(chip->comm_page->control_register) &
308 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
310 switch (clock) {
312 chip->input_clock = ECHO_CLOCK_INTERNAL;
313 return set_sample_rate(chip, chip->sample_rate);
315 if (chip->digital_mode == DIGITAL_MODE_ADAT)
316 return -EAGAIN;
317 spin_unlock_irq(&chip->lock);
320 spin_lock_irq(&chip->lock);
330 spin_unlock_irq(&chip->lock);
333 spin_lock_irq(&chip->lock);
343 dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n");
344 if (chip->digital_mode != DIGITAL_MODE_ADAT)
345 return -EAGAIN;
350 dev_err(chip->card->dev,
351 "Input clock 0x%x not supported for Mona\n", clock);
352 return -EINVAL;
355 chip->input_clock = clock;
361 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
366 /* Set clock to "internal" if it's not compatible with the new mode */
368 switch (mode) {
371 if (chip->input_clock == ECHO_CLOCK_ADAT)
375 if (chip->input_clock == ECHO_CLOCK_SPDIF)
379 dev_err(chip->card->dev,
380 "Digital mode not supported: %d\n", mode);
381 return -EINVAL;
384 guard(spinlock_irq)(&chip->lock);
387 chip->sample_rate = 48000;
391 /* Clear the current digital mode */
392 control_reg = le32_to_cpu(chip->comm_page->control_register);
396 switch (mode) {
406 if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
407 chip->asic_code == FW_MONA_301_1_ASIC96) {
418 chip->digital_mode = mode;
420 dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);