Lines Matching +full:clock +full:- +full:mode
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA.
25 Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
44 return -ENODEV;
48 dev_err(chip->card->dev,
49 "init_hw - could not initialize DSP comm page\n");
53 chip->device_id = device_id;
54 chip->subdevice_id = subdevice_id;
55 chip->bad_board = true;
56 chip->has_midi = true;
57 chip->dsp_code_to_load = FW_LAYLA24_DSP;
58 chip->input_clock_types =
61 chip->digital_modes =
69 chip->bad_board = false;
82 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
83 chip->professional_spdif = false;
84 chip->digital_in_automute = true;
94 /* Map the DSP clock detect bits to the generic driver clock detect bits */
95 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
119 if (chip->asic_loaded)
132 chip->asic_code = FW_LAYLA24_2S_ASIC;
149 /* Set up the control register if the load succeeded -
150 48 kHz, internal clock, S/PDIF RCA mode */
162 u32 control_reg, clock, base_rate;
165 chip->digital_mode == DIGITAL_MODE_ADAT))
166 return -EINVAL;
168 /* Only set the clock for internal mode. */
169 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
170 dev_warn(chip->card->dev,
171 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
173 chip->comm_page->sample_rate = cpu_to_le32(rate);
174 chip->sample_rate = rate;
179 control_reg = le32_to_cpu(chip->comm_page->control_register);
182 clock = 0;
186 clock = GML_96KHZ;
189 clock = GML_88KHZ;
192 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
195 clock = GML_44KHZ;
196 /* Professional mode */
198 clock |= GML_SPDIF_SAMPLE_RATE0;
201 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
205 clock = GML_22KHZ;
208 clock = GML_16KHZ;
211 clock = GML_11KHZ;
214 clock = GML_8KHZ;
217 /* If this is a non-standard rate, then the driver needs to
218 use Layla24's special "continuous frequency" mode */
219 clock = LAYLA24_CONTINUOUS_CLOCK;
231 return -EIO;
233 chip->comm_page->sample_rate =
234 cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2);
240 control_reg |= clock;
242 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
243 chip->sample_rate = rate;
244 dev_dbg(chip->card->dev,
245 "set_sample_rate: %d clock %d\n", rate, control_reg);
252 static int set_input_clock(struct echoaudio *chip, u16 clock)
256 /* Mask off the clock select bits */
257 control_reg = le32_to_cpu(chip->comm_page->control_register) &
259 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
261 /* Pick the new clock */
262 switch (clock) {
264 chip->input_clock = ECHO_CLOCK_INTERNAL;
265 return set_sample_rate(chip, chip->sample_rate);
267 if (chip->digital_mode == DIGITAL_MODE_ADAT)
268 return -EAGAIN;
281 if (chip->digital_mode != DIGITAL_MODE_ADAT)
282 return -EAGAIN;
287 dev_err(chip->card->dev,
288 "Input clock 0x%x not supported for Layla24\n", clock);
289 return -EINVAL;
292 chip->input_clock = clock;
298 /* Depending on what digital mode you want, Layla24 needs different ASICs
299 loaded. This function checks the ASIC needed for the new mode and sees
306 if (asic != chip->asic_code) {
307 monitors = kmemdup(chip->comm_page->monitors,
310 return -ENOMEM;
312 memset(chip->comm_page->monitors, ECHOGAIN_MUTED,
318 memcpy(chip->comm_page->monitors, monitors,
321 return -EIO;
323 chip->asic_code = asic;
324 memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);
333 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
339 /* Set clock to "internal" if it's not compatible with the new mode */
341 switch (mode) {
344 if (chip->input_clock == ECHO_CLOCK_ADAT)
349 if (chip->input_clock == ECHO_CLOCK_SPDIF)
354 dev_err(chip->card->dev,
355 "Digital mode not supported: %d\n", mode);
356 return -EINVAL;
360 chip->sample_rate = 48000;
361 guard(spinlock_irq)(&chip->lock);
367 return -EIO;
369 guard(spinlock_irq)(&chip->lock);
372 control_reg = le32_to_cpu(chip->comm_page->control_register);
375 switch (mode) {
391 chip->digital_mode = mode;
393 dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);