126 	u32 control_reg;  in load_asic()  local
156 		control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;  in load_asic()
157 		err = write_control_reg(chip, control_reg, true);  in load_asic()
166 	u32 control_reg, clock;  in set_sample_rate()  local
184 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
185 	control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;  in set_sample_rate()
200 		if (control_reg & GML_SPDIF_PRO_MODE)  in set_sample_rate()
225 	control_reg |= clock;  in set_sample_rate()
231 	return write_control_reg(chip, control_reg, false);  in set_sample_rate()
238 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
242 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
253 		control_reg |= GML_SPDIF_CLOCK;  in set_input_clock()
255 			control_reg |= GML_DOUBLE_SPEED_MODE;  in set_input_clock()
257 			control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
262 		control_reg |= GML_ADAT_CLOCK;  in set_input_clock()
263 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
266 		control_reg |= GML_ESYNC_CLOCK;  in set_input_clock()
267 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in set_input_clock()
270 		control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;  in set_input_clock()
279 	return write_control_reg(chip, control_reg, true);  in set_input_clock()
286 	u32 control_reg;  in dsp_set_digital_mode()  local
316 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
317 	control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
322 		control_reg |= GML_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
327 			control_reg |= GML_SPDIF_CDROM_MODE;  in dsp_set_digital_mode()
333 		control_reg |= GML_ADAT_MODE;  in dsp_set_digital_mode()
334 		control_reg &= ~GML_DOUBLE_SPEED_MODE;  in dsp_set_digital_mode()
338 	err = write_control_reg(chip, control_reg, true);  in dsp_set_digital_mode()