Lines Matching +full:clock +full:- +full:mode
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV;
49 dev_err(chip->card->dev,
50 "init_hw - could not initialize DSP comm page\n");
54 chip->device_id = device_id;
55 chip->subdevice_id = subdevice_id;
56 chip->bad_board = true;
57 chip->input_clock_types =
63 if (chip->device_id == DEVICE_ID_56361) {
64 chip->dsp_code_to_load = FW_GINA24_361_DSP;
65 chip->digital_modes =
70 chip->dsp_code_to_load = FW_GINA24_301_DSP;
71 chip->digital_modes =
81 chip->bad_board = false;
90 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
91 chip->professional_spdif = false;
92 chip->digital_in_automute = true;
102 /* Map the DSP clock detect bits to the generic driver clock
104 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
130 if (chip->asic_loaded)
137 if (chip->device_id == DEVICE_ID_56361)
146 chip->asic_code = asic;
153 /* Set up the control register if the load succeeded -
154 48 kHz, internal clock, S/PDIF RCA mode */
166 u32 control_reg, clock;
169 chip->digital_mode == DIGITAL_MODE_ADAT))
170 return -EINVAL;
172 /* Only set the clock for internal mode. */
173 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
174 dev_warn(chip->card->dev,
175 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
177 chip->comm_page->sample_rate = cpu_to_le32(rate);
178 chip->sample_rate = rate;
182 clock = 0;
184 control_reg = le32_to_cpu(chip->comm_page->control_register);
189 clock = GML_96KHZ;
192 clock = GML_88KHZ;
195 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
198 clock = GML_44KHZ;
199 /* Professional mode ? */
201 clock |= GML_SPDIF_SAMPLE_RATE0;
204 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
208 clock = GML_22KHZ;
211 clock = GML_16KHZ;
214 clock = GML_11KHZ;
217 clock = GML_8KHZ;
220 dev_err(chip->card->dev,
222 return -EINVAL;
225 control_reg |= clock;
227 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
228 chip->sample_rate = rate;
229 dev_dbg(chip->card->dev, "set_sample_rate: %d clock %d\n", rate, clock);
236 static int set_input_clock(struct echoaudio *chip, u16 clock)
241 /* Mask off the clock select bits */
242 control_reg = le32_to_cpu(chip->comm_page->control_register) &
244 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
246 switch (clock) {
248 chip->input_clock = ECHO_CLOCK_INTERNAL;
249 return set_sample_rate(chip, chip->sample_rate);
251 if (chip->digital_mode == DIGITAL_MODE_ADAT)
252 return -EAGAIN;
260 if (chip->digital_mode != DIGITAL_MODE_ADAT)
261 return -EAGAIN;
273 dev_err(chip->card->dev,
274 "Input clock 0x%x not supported for Gina24\n", clock);
275 return -EINVAL;
278 chip->input_clock = clock;
284 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
289 /* Set clock to "internal" if it's not compatible with the new mode */
291 switch (mode) {
295 if (chip->input_clock == ECHO_CLOCK_ADAT)
299 if (chip->input_clock == ECHO_CLOCK_SPDIF)
303 dev_err(chip->card->dev,
304 "Digital mode not supported: %d\n", mode);
305 return -EINVAL;
308 guard(spinlock_irq)(&chip->lock);
311 chip->sample_rate = 48000;
315 /* Clear the current digital mode */
316 control_reg = le32_to_cpu(chip->comm_page->control_register);
320 switch (mode) {
325 /* '361 Gina24 cards do not have the S/PDIF CD-ROM mode */
326 if (chip->device_id == DEVICE_ID_56301)
341 chip->digital_mode = mode;
343 dev_dbg(chip->card->dev,
344 "set_digital_mode to %d\n", chip->digital_mode);