Lines Matching +full:clock +full:- +full:mode
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 return -EIO;
43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED);
44 chip->asic_loaded = false;
49 chip->dsp_code = NULL;
50 return -EIO;
53 box_status = le32_to_cpu(chip->comm_page->ext_box_status);
54 dev_dbg(chip->card->dev, "box_status=%x\n", box_status);
56 return -ENODEV;
58 chip->asic_loaded = true;
66 return le32_to_cpu(chip->comm_page->e3g_frq_register);
79 return -EIO;
81 dev_dbg(chip->card->dev,
87 if (ctl_reg != chip->comm_page->control_register ||
88 frq_reg != chip->comm_page->e3g_frq_register || force) {
89 chip->comm_page->e3g_frq_register = frq_reg;
90 chip->comm_page->control_register = ctl_reg;
95 dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n");
101 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
102 static int set_digital_mode(struct echoaudio *chip, u8 mode)
107 /* All audio channels must be closed before changing the digital mode */
108 if (snd_BUG_ON(chip->pipe_alloc_mask))
109 return -EAGAIN;
111 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
112 return -EINVAL;
114 previous_mode = chip->digital_mode;
115 err = dsp_set_digital_mode(chip, mode);
117 /* If we successfully changed the digital mode from or to ADAT,
120 if (err >= 0 && previous_mode != mode &&
121 (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
122 guard(spinlock_irq)(&chip->lock);
126 chip->monitor_gain[o][i]);
130 set_input_gain(chip, i, chip->input_gain[i]);
135 set_output_gain(chip, o, chip->output_gain[o]);
153 if (chip->professional_spdif)
161 if (chip->professional_spdif)
164 if (chip->non_audio_spdif)
180 control_reg = le32_to_cpu(chip->comm_page->control_register);
181 chip->professional_spdif = prof;
182 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
190 disconnects clock inputs. You should use this information to determine which
196 /* Map the DSP clock detect bits to the generic driver clock
198 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
205 switch(chip->digital_mode) {
226 if (chip->asic_loaded)
236 chip->asic_code = FW_3G_ASIC;
243 /* Set up the control register if the load succeeded -
244 * 48 kHz, internal clock, S/PDIF RCA mode */
259 u32 control_reg, clock, base_rate, frq_reg;
261 /* Only set the clock for internal mode. */
262 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
263 dev_warn(chip->card->dev,
264 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
266 chip->comm_page->sample_rate = cpu_to_le32(rate);
267 chip->sample_rate = rate;
268 set_input_clock(chip, chip->input_clock);
273 chip->digital_mode == DIGITAL_MODE_ADAT))
274 return -EINVAL;
276 control_reg = le32_to_cpu(chip->comm_page->control_register);
281 clock = E3G_96KHZ;
284 clock = E3G_88KHZ;
287 clock = E3G_48KHZ;
290 clock = E3G_44KHZ;
293 clock = E3G_32KHZ;
296 clock = E3G_CONTINUOUS_CLOCK;
298 clock |= E3G_DOUBLE_SPEED_MODE;
302 control_reg |= clock;
311 frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
315 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
316 chip->sample_rate = rate;
317 dev_dbg(chip->card->dev,
318 "SetSampleRate: %d clock %x\n", rate, control_reg);
320 /* Tell the DSP about it - DSP reads both control reg & freq reg */
326 /* Set the sample clock source to internal, S/PDIF, ADAT */
327 static int set_input_clock(struct echoaudio *chip, u16 clock)
332 /* Mask off the clock select bits */
333 control_reg = le32_to_cpu(chip->comm_page->control_register) &
335 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
337 switch (clock) {
339 chip->input_clock = ECHO_CLOCK_INTERNAL;
340 return set_sample_rate(chip, chip->sample_rate);
342 if (chip->digital_mode == DIGITAL_MODE_ADAT)
343 return -EAGAIN;
351 if (chip->digital_mode != DIGITAL_MODE_ADAT)
352 return -EAGAIN;
364 dev_err(chip->card->dev,
365 "Input clock 0x%x not supported for Echo3G\n", clock);
366 return -EINVAL;
369 chip->input_clock = clock;
375 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
380 /* Set clock to "internal" if it's not compatible with the new mode */
382 switch (mode) {
385 if (chip->input_clock == ECHO_CLOCK_ADAT)
389 if (chip->input_clock == ECHO_CLOCK_SPDIF)
393 dev_err(chip->card->dev,
394 "Digital mode not supported: %d\n", mode);
395 return -EINVAL;
398 guard(spinlock_irq)(&chip->lock);
401 chip->sample_rate = 48000;
405 /* Clear the current digital mode */
406 control_reg = le32_to_cpu(chip->comm_page->control_register);
410 switch (mode) {
426 chip->digital_mode = mode;
428 dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode);