Lines Matching defs:control_reg

144 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
146 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
150 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
154 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;
157 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;
162 		control_reg |= E3G_SPDIF_PRO_MODE;
165 		control_reg |= E3G_SPDIF_NOT_AUDIO;
167 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
170 	return control_reg;
178 	u32 control_reg;
180 	control_reg = le32_to_cpu(chip->comm_page->control_register);
182 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
183 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
259 	u32 control_reg, clock, base_rate, frq_reg;
276 	control_reg = le32_to_cpu(chip->comm_page->control_register);
277 	control_reg &= E3G_CLOCK_CLEAR_MASK;
302 	control_reg |= clock;
303 	control_reg = set_spdif_bits(chip, control_reg, rate);
318 		"SetSampleRate: %d clock %x\n", rate, control_reg);
321 	return write_control_reg(chip, control_reg, frq_reg, 0);
329 	u32 control_reg, clocks_from_dsp;
333 	control_reg = le32_to_cpu(chip->comm_page->control_register) &
344 		control_reg |= E3G_SPDIF_CLOCK;
346 			control_reg |= E3G_DOUBLE_SPEED_MODE;
348 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
353 		control_reg |= E3G_ADAT_CLOCK;
354 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;
357 		control_reg |= E3G_WORD_CLOCK;
359 			control_reg |= E3G_DOUBLE_SPEED_MODE;
361 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
370 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
377 	u32 control_reg;
406 	control_reg = le32_to_cpu(chip->comm_page->control_register);
407 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
412 		control_reg |= E3G_SPDIF_OPTICAL_MODE;
418 		control_reg |= E3G_ADAT_MODE;
419 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */
423 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);