Lines Matching +full:0 +full:xec
47 #define SRCCTL_STATE 0x00000007
48 #define SRCCTL_BM 0x00000008
49 #define SRCCTL_RSR 0x00000030
50 #define SRCCTL_SF 0x000001C0
51 #define SRCCTL_WR 0x00000200
52 #define SRCCTL_PM 0x00000400
53 #define SRCCTL_ROM 0x00001800
54 #define SRCCTL_VO 0x00002000
55 #define SRCCTL_ST 0x00004000
56 #define SRCCTL_IE 0x00008000
57 #define SRCCTL_ILSZ 0x000F0000
58 #define SRCCTL_BP 0x00100000
60 #define SRCCCR_CISZ 0x000007FF
61 #define SRCCCR_CWA 0x001FF800
62 #define SRCCCR_D 0x00200000
63 #define SRCCCR_RS 0x01C00000
64 #define SRCCCR_NAL 0x3E000000
65 #define SRCCCR_RA 0xC0000000
67 #define SRCCA_CA 0x03FFFFFF
68 #define SRCCA_RS 0x1C000000
69 #define SRCCA_NAL 0xE0000000
71 #define SRCSA_SA 0x03FFFFFF
73 #define SRCLA_LA 0x03FFFFFF
77 #define MPRLH_PITCH 0xFFFFFFFF
128 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000
166 return 0; in src_get_rsc_ctrl_blk()
173 return 0; in src_put_rsc_ctrl_blk()
182 return 0; in src_set_state()
191 return 0; in src_set_bm()
200 return 0; in src_set_rsr()
209 return 0; in src_set_sf()
218 return 0; in src_set_wr()
227 return 0; in src_set_pm()
236 return 0; in src_set_rom()
245 return 0; in src_set_vo()
254 return 0; in src_set_st()
263 return 0; in src_set_ie()
272 return 0; in src_set_ilsz()
281 return 0; in src_set_bp()
290 return 0; in src_set_cisz()
299 return 0; in src_set_ca()
308 return 0; in src_set_sa()
317 return 0; in src_set_la()
326 return 0; in src_set_pitch()
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); in src_set_clear_zbufs()
332 return 0; in src_set_clear_zbufs()
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); in src_set_dirty()
338 return 0; in src_set_dirty()
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); in src_set_dirty_all()
344 return 0; in src_set_dirty_all()
350 #define AR_PARAM_SRC_OFFSET 0x60
366 for (i = 0; i < 8; i++) in src_commit_write()
367 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0); in src_commit_write()
369 for (i = 0; i < 4; i++) in src_commit_write()
370 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0); in src_commit_write()
372 for (i = 0; i < 8; i++) in src_commit_write()
373 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0); in src_commit_write()
375 ctl->dirty.bf.czbfs = 0; in src_commit_write()
384 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3); in src_commit_write()
385 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0); in src_commit_write()
386 ctl->dirty.bf.mpr = 0; in src_commit_write()
389 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa); in src_commit_write()
390 ctl->dirty.bf.sa = 0; in src_commit_write()
393 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la); in src_commit_write()
394 ctl->dirty.bf.la = 0; in src_commit_write()
397 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca); in src_commit_write()
398 ctl->dirty.bf.ca = 0; in src_commit_write()
402 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0); in src_commit_write()
405 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr); in src_commit_write()
406 ctl->dirty.bf.ccr = 0; in src_commit_write()
409 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl); in src_commit_write()
410 ctl->dirty.bf.ctl = 0; in src_commit_write()
413 return 0; in src_commit_write()
420 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100); in src_get_ca()
421 ctl->dirty.bf.ca = 0; in src_get_ca()
433 return 0x20; in src_dirty_conj_mask()
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0); in src_mgr_enbs_src()
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); in src_mgr_enbs_src()
441 return 0; in src_mgr_enbs_src()
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); in src_mgr_enb_src()
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); in src_mgr_enb_src()
448 return 0; in src_mgr_enb_src()
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); in src_mgr_dsb_src()
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); in src_mgr_dsb_src()
455 return 0; in src_mgr_dsb_src()
467 } while (ret & 0x1); in src_mgr_commit_write()
469 ctl->dirty.bf.enbsa = 0; in src_mgr_commit_write()
471 for (i = 0; i < 8; i++) { in src_mgr_commit_write()
472 if ((ctl->dirty.data & (0x1 << i))) { in src_mgr_commit_write()
473 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]); in src_mgr_commit_write()
474 ctl->dirty.data &= ~(0x1 << i); in src_mgr_commit_write()
478 return 0; in src_mgr_commit_write()
492 return 0; in src_mgr_get_ctrl_blk()
499 return 0; in src_mgr_put_ctrl_blk()
513 return 0; in srcimp_mgr_get_ctrl_blk()
520 return 0; in srcimp_mgr_put_ctrl_blk()
529 return 0; in srcimp_mgr_set_imaparc()
538 return 0; in srcimp_mgr_set_imapuser()
547 return 0; in srcimp_mgr_set_imapnxt()
556 return 0; in srcimp_mgr_set_imapaddr()
564 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100, in srcimp_mgr_commit_write()
566 ctl->dirty.bf.srcimap = 0; in srcimp_mgr_commit_write()
569 return 0; in srcimp_mgr_commit_write()
576 #define AMOPLO_M 0x00000003
577 #define AMOPLO_X 0x0003FFF0
578 #define AMOPLO_Y 0xFFFC0000
580 #define AMOPHI_SADR 0x000000FF
581 #define AMOPHI_SE 0x80000000
606 return 0; in amixer_set_mode()
612 return 0; in amixer_set_iv()
621 return 0; in amixer_set_x()
630 return 0; in amixer_set_y()
639 return 0; in amixer_set_sadr()
648 return 0; in amixer_set_se()
653 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); in amixer_set_dirty()
654 return 0; in amixer_set_dirty()
659 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); in amixer_set_dirty_all()
660 return 0; in amixer_set_dirty_all()
669 ctl->dirty.bf.amoplo = 0; in amixer_commit_write()
671 ctl->dirty.bf.amophi = 0; in amixer_commit_write()
674 return 0; in amixer_commit_write()
700 return 0; in amixer_rsc_get_ctrl_blk()
707 return 0; in amixer_rsc_put_ctrl_blk()
721 return 0; in amixer_mgr_get_ctrl_blk()
728 return 0; in amixer_mgr_put_ctrl_blk()
736 #define SRTCTL_SRCR 0x000000FF
737 #define SRTCTL_SRCL 0x0000FF00
738 #define SRTCTL_RSR 0x00030000
739 #define SRTCTL_DRAT 0x000C0000
740 #define SRTCTL_RLE 0x10000000
741 #define SRTCTL_RLP 0x20000000
742 #define SRTCTL_EC 0x40000000
743 #define SRTCTL_ET 0x80000000
776 #define AIM_ARC 0x00000FFF
777 #define AIM_NXT 0x007F0000
785 #define I2SCTL_EA 0x00000004
786 #define I2SCTL_EI 0x00000010
789 #define SPOCTL_OE 0x00000001
790 #define SPOCTL_OS 0x0000000E
791 #define SPOCTL_RIV 0x00000010
792 #define SPOCTL_LIV 0x00000020
793 #define SPOCTL_SR 0x000000C0
796 #define SPICTL_EN 0x00000001
797 #define SPICTL_I24 0x00000002
798 #define SPICTL_IB 0x00000004
799 #define SPICTL_SM 0x00000008
800 #define SPICTL_VM 0x00000010
830 return 0; in dai_srt_set_srcr()
839 return 0; in dai_srt_set_srcl()
848 return 0; in dai_srt_set_rsr()
857 return 0; in dai_srt_set_drat()
864 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0); in dai_srt_set_ec()
866 return 0; in dai_srt_set_ec()
873 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0); in dai_srt_set_et()
875 return 0; in dai_srt_set_et()
885 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl); in dai_commit_write()
890 ctl->dirty.bf.srtctl = 0; in dai_commit_write()
893 return 0; in dai_commit_write()
907 return 0; in dai_get_ctrl_blk()
914 return 0; in dai_put_ctrl_blk()
921 return 0; in dao_set_spos()
931 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos); in dao_commit_write()
933 ctl->dirty.bf.spos = 0; in dao_commit_write()
936 return 0; in dao_commit_write()
942 return 0; in dao_get_spos()
956 return 0; in dao_get_ctrl_blk()
963 return 0; in dao_put_ctrl_blk()
973 ctl->dirty.bf.spictl |= (0x1 << idx); in daio_mgr_enb_dai()
978 ctl->dirty.bf.i2sictl |= (0x1 << idx); in daio_mgr_enb_dai()
980 return 0; in daio_mgr_enb_dai()
989 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0); in daio_mgr_dsb_dai()
990 ctl->dirty.bf.spictl |= (0x1 << idx); in daio_mgr_dsb_dai()
994 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0); in daio_mgr_dsb_dai()
995 ctl->dirty.bf.i2sictl |= (0x1 << idx); in daio_mgr_dsb_dai()
997 return 0; in daio_mgr_dsb_dai()
1007 ctl->dirty.bf.spoctl |= (0x1 << idx); in daio_mgr_enb_dao()
1012 ctl->dirty.bf.i2soctl |= (0x1 << idx); in daio_mgr_enb_dao()
1014 return 0; in daio_mgr_enb_dao()
1023 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0); in daio_mgr_dsb_dao()
1024 ctl->dirty.bf.spoctl |= (0x1 << idx); in daio_mgr_dsb_dao()
1028 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0); in daio_mgr_dsb_dao()
1029 ctl->dirty.bf.i2soctl |= (0x1 << idx); in daio_mgr_dsb_dao()
1031 return 0; in daio_mgr_dsb_dao()
1040 switch ((conf & 0x7)) { in daio_mgr_dao_init()
1041 case 0: in daio_mgr_dao_init()
1045 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0); in daio_mgr_dao_init()
1057 (conf >> 4) & 0x1); /* Non-audio */ in daio_mgr_dao_init()
1059 (conf >> 4) & 0x1); /* Non-audio */ in daio_mgr_dao_init()
1061 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */ in daio_mgr_dao_init()
1063 ctl->dirty.bf.spoctl |= (0x1 << idx); in daio_mgr_dao_init()
1068 return 0; in daio_mgr_dao_init()
1077 return 0; in daio_mgr_set_imaparc()
1086 return 0; in daio_mgr_set_imapnxt()
1095 return 0; in daio_mgr_set_imapaddr()
1104 for (i = 0; i < 4; i++) { in daio_mgr_commit_write()
1105 if ((ctl->dirty.bf.i2sictl & (0x1 << i))) in daio_mgr_commit_write()
1106 ctl->dirty.bf.i2sictl &= ~(0x1 << i); in daio_mgr_commit_write()
1108 if ((ctl->dirty.bf.i2soctl & (0x1 << i))) in daio_mgr_commit_write()
1109 ctl->dirty.bf.i2soctl &= ~(0x1 << i); in daio_mgr_commit_write()
1115 for (i = 0; i < 4; i++) { in daio_mgr_commit_write()
1116 if ((ctl->dirty.bf.spoctl & (0x1 << i))) in daio_mgr_commit_write()
1117 ctl->dirty.bf.spoctl &= ~(0x1 << i); in daio_mgr_commit_write()
1123 for (i = 0; i < 4; i++) { in daio_mgr_commit_write()
1124 if ((ctl->dirty.bf.spictl & (0x1 << i))) in daio_mgr_commit_write()
1125 ctl->dirty.bf.spictl &= ~(0x1 << i); in daio_mgr_commit_write()
1133 ctl->dirty.bf.daoimap = 0; in daio_mgr_commit_write()
1136 return 0; in daio_mgr_commit_write()
1154 return 0; in daio_mgr_get_ctrl_blk()
1161 return 0; in daio_mgr_put_ctrl_blk()
1167 hw_write_20kx(hw, GIE, enable ? IT_INT : 0); in set_timer_irq()
1168 return 0; in set_timer_irq()
1176 return 0; in set_timer_tick()
1210 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */ in hw_daio_init()
1213 i2sorg &= 0xfffffffc; in hw_daio_init()
1218 hw_write_20kx(hw, SPOCTL, 0x0); in hw_daio_init()
1219 spdorg = 0x05; in hw_daio_init()
1224 spdorg |= (0x0 << 6); in hw_daio_init()
1228 spdorg |= (0x1 << 6); in hw_daio_init()
1232 spdorg |= (0x2 << 6); in hw_daio_init()
1244 hw_write_20kx(hw, SPICTL, 0x0); in hw_daio_init()
1246 spdorg = 0x0a0a0a0a; in hw_daio_init()
1250 return 0; in hw_daio_init()
1260 if ((~0UL) == info->vm_pgt_phys) { in hw_trn_init()
1266 trnctl = 0x13; /* 32-bit, 4k-size page */ in hw_trn_init()
1271 #if 0 /* Only 4k h/w pages for simplicitiy */ in hw_trn_init()
1279 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */ in hw_trn_init()
1281 return 0; in hw_trn_init()
1285 #define GCTL_EAC 0x00000001
1286 #define GCTL_EAI 0x00000002
1287 #define GCTL_BEP 0x00000004
1288 #define GCTL_BES 0x00000008
1289 #define GCTL_DSP 0x00000010
1290 #define GCTL_DBP 0x00000020
1291 #define GCTL_ABP 0x00000040
1292 #define GCTL_TBP 0x00000080
1293 #define GCTL_SBP 0x00000100
1294 #define GCTL_FBP 0x00000200
1295 #define GCTL_XA 0x00000400
1296 #define GCTL_ET 0x00000800
1297 #define GCTL_PR 0x00001000
1298 #define GCTL_MRL 0x00002000
1299 #define GCTL_SDE 0x00004000
1300 #define GCTL_SDI 0x00008000
1301 #define GCTL_SM 0x00010000
1302 #define GCTL_SR 0x00020000
1303 #define GCTL_SD 0x00040000
1304 #define GCTL_SE 0x00080000
1305 #define GCTL_AID 0x00100000
1312 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731; in hw_pll_init()
1313 for (i = 0; i < 3; i++) { in hw_pll_init()
1325 return 0; in hw_pll_init()
1334 set_field(&gctl, GCTL_EAI, 0); in hw_auto_init()
1339 for (i = 0; i < 400000; i++) { in hw_auto_init()
1349 return 0; in hw_auto_init()
1354 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) in i2c_unlock()
1355 return 0; in i2c_unlock()
1357 hw_write_pci(hw, 0xcc, 0x8c); in i2c_unlock()
1358 hw_write_pci(hw, 0xcc, 0x0e); in i2c_unlock()
1359 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) in i2c_unlock()
1360 return 0; in i2c_unlock()
1362 hw_write_pci(hw, 0xcc, 0xee); in i2c_unlock()
1363 hw_write_pci(hw, 0xcc, 0xaa); in i2c_unlock()
1364 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) in i2c_unlock()
1365 return 0; in i2c_unlock()
1372 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) in i2c_lock()
1373 hw_write_pci(hw, 0xcc, 0x00); in i2c_lock()
1381 ret = hw_read_pci(hw, 0xEC); in i2c_write()
1382 } while (!(ret & 0x800000)); in i2c_write()
1383 hw_write_pci(hw, 0xE0, device); in i2c_write()
1384 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff)); in i2c_write()
1399 ret = hw_read_pci(hw, 0xEC); in hw_reset_dac()
1400 } while (!(ret & 0x800000)); in hw_reset_dac()
1401 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ in hw_reset_dac()
1404 for (i = 0; i < 2; i++) { in hw_reset_dac()
1408 gpioorg &= 0xfffd; in hw_reset_dac()
1411 hw_write_20kx(hw, GPIO, gpioorg | 0x2); in hw_reset_dac()
1414 i2c_write(hw, 0x00180080, 0x01, 0x80); in hw_reset_dac()
1415 i2c_write(hw, 0x00180080, 0x02, 0x10); in hw_reset_dac()
1419 return 0; in hw_reset_dac()
1431 gpioorg &= 0xffbf; /* set GPIO6 to low */ in hw_dac_init()
1434 return 0; in hw_dac_init()
1439 gpioorg &= 0xffbf; in hw_dac_init()
1447 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ in hw_dac_init()
1449 ret = hw_read_pci(hw, 0xEC); in hw_dac_init()
1450 } while (!(ret & 0x800000)); in hw_dac_init()
1454 data = 0x24; in hw_dac_init()
1457 data = 0x25; in hw_dac_init()
1460 data = 0x26; in hw_dac_init()
1463 data = 0x24; in hw_dac_init()
1467 i2c_write(hw, 0x00180080, 0x06, data); in hw_dac_init()
1468 i2c_write(hw, 0x00180080, 0x09, data); in hw_dac_init()
1469 i2c_write(hw, 0x00180080, 0x0c, data); in hw_dac_init()
1470 i2c_write(hw, 0x00180080, 0x0f, data); in hw_dac_init()
1476 gpioorg = gpioorg | 0x40; in hw_dac_init()
1479 return 0; in hw_dac_init()
1486 return 0; in is_adc_input_selected_SB055x()
1496 data = ((data & (0x1<<7)) && (data & (0x1<<8))); in is_adc_input_selected_SBx()
1499 data = (!(data & (0x1<<7)) && (data & (0x1<<8))); in is_adc_input_selected_SBx()
1502 data = (!(data & (0x1<<8))); in is_adc_input_selected_SBx()
1505 data = 0; in is_adc_input_selected_SBx()
1517 data = (data & (0x1 << 7)) ? 1 : 0; in is_adc_input_selected_hendrix()
1520 data = (data & (0x1 << 7)) ? 0 : 1; in is_adc_input_selected_hendrix()
1523 data = 0; in is_adc_input_selected_hendrix()
1557 data &= 0xec73; in adc_input_select_SB055x()
1560 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ; in adc_input_select_SB055x()
1561 data |= boost ? (0x1<<2) : 0; in adc_input_select_SB055x()
1564 data |= (0x1<<8); in adc_input_select_SB055x()
1567 data |= (0x1<<8) | (0x1<<12); in adc_input_select_SB055x()
1570 data |= (0x1<<12); /* set to digital */ in adc_input_select_SB055x()
1578 return 0; in adc_input_select_SB055x()
1593 ret = hw_read_pci(hw, 0xEC); in adc_input_select_SBx()
1594 } while (!(ret & 0x800000)); /* i2c ready poll */ in adc_input_select_SBx()
1596 hw_write_pci(hw, 0xEC, 0x05); in adc_input_select_SBx()
1601 data |= ((0x1 << 7) | (0x1 << 8)); in adc_input_select_SBx()
1602 i2c_data = 0x1; /* Mic-in */ in adc_input_select_SBx()
1605 data &= ~(0x1 << 7); in adc_input_select_SBx()
1606 data |= (0x1 << 8); in adc_input_select_SBx()
1607 i2c_data = 0x2; /* Line-in */ in adc_input_select_SBx()
1610 data &= ~(0x1 << 8); in adc_input_select_SBx()
1611 i2c_data = 0x0; /* set to Digital */ in adc_input_select_SBx()
1618 i2c_write(hw, 0x001a0080, 0x2a, i2c_data); in adc_input_select_SBx()
1620 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ in adc_input_select_SBx()
1621 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ in adc_input_select_SBx()
1623 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ in adc_input_select_SBx()
1624 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ in adc_input_select_SBx()
1629 return 0; in adc_input_select_SBx()
1643 ret = hw_read_pci(hw, 0xEC); in adc_input_select_hendrix()
1644 } while (!(ret & 0x800000)); /* i2c ready poll */ in adc_input_select_hendrix()
1646 hw_write_pci(hw, 0xEC, 0x05); in adc_input_select_hendrix()
1651 data |= (0x1 << 7); in adc_input_select_hendrix()
1652 i2c_data = 0x1; /* Mic-in */ in adc_input_select_hendrix()
1655 data &= ~(0x1 << 7); in adc_input_select_hendrix()
1656 i2c_data = 0x2; /* Line-in */ in adc_input_select_hendrix()
1663 i2c_write(hw, 0x001a0080, 0x2a, i2c_data); in adc_input_select_hendrix()
1665 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ in adc_input_select_hendrix()
1666 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ in adc_input_select_hendrix()
1668 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ in adc_input_select_hendrix()
1669 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ in adc_input_select_hendrix()
1674 return 0; in adc_input_select_hendrix()
1705 input_source = 0x100; /* default to analog */ in adc_init_SBx()
1708 adcdata = 0x1; in adc_init_SBx()
1709 input_source = 0x180; /* set GPIO7 to select Mic */ in adc_init_SBx()
1712 adcdata = 0x2; in adc_init_SBx()
1715 adcdata = 0x4; in adc_init_SBx()
1718 adcdata = 0x8; in adc_init_SBx()
1721 adcdata = 0x0; in adc_init_SBx()
1722 input_source = 0x0; /* set to Digital */ in adc_init_SBx()
1725 adcdata = 0x0; in adc_init_SBx()
1733 ret = hw_read_pci(hw, 0xEC); in adc_init_SBx()
1734 } while (!(ret & 0x800000)); /* i2c ready poll */ in adc_init_SBx()
1735 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ in adc_init_SBx()
1737 i2c_write(hw, 0x001a0080, 0x0e, 0x08); in adc_init_SBx()
1738 i2c_write(hw, 0x001a0080, 0x18, 0x0a); in adc_init_SBx()
1739 i2c_write(hw, 0x001a0080, 0x28, 0x86); in adc_init_SBx()
1740 i2c_write(hw, 0x001a0080, 0x2a, adcdata); in adc_init_SBx()
1743 i2c_write(hw, 0x001a0080, 0x1c, 0xf7); in adc_init_SBx()
1744 i2c_write(hw, 0x001a0080, 0x1e, 0xf7); in adc_init_SBx()
1746 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); in adc_init_SBx()
1747 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); in adc_init_SBx()
1750 if (!(hw_read_20kx(hw, ID0) & 0x100)) in adc_init_SBx()
1751 i2c_write(hw, 0x001a0080, 0x16, 0x26); in adc_init_SBx()
1756 gpioorg &= 0xfe7f; in adc_init_SBx()
1760 return 0; in adc_init_SBx()
1777 cap.dedicated_mic = 0; in hw_capabilities()
1778 cap.output_switch = 0; in hw_capabilities()
1779 cap.mic_source_switch = 0; in hw_capabilities()
1786 #define UAA_CFG_PWRSTATUS 0x44
1787 #define UAA_CFG_SPACE_FLAG 0xA0
1788 #define UAA_CORE_CHANGE 0x3FFC
1794 unsigned int data[4] = {0}; in uaa_to_xfi()
1807 io_base = pci_resource_start(pci, 0); in uaa_to_xfi()
1808 mem_base = ioremap(io_base, pci_resource_len(pci, 0)); in uaa_to_xfi()
1813 for (i = 0; i < 4; i++) in uaa_to_xfi()
1817 if (data[0] == CTLA) { in uaa_to_xfi()
1821 } else if (data[0] == CTLZ) { in uaa_to_xfi()
1824 } else if (data[0] == CTLL) { in uaa_to_xfi()
1828 is_uaa = 0; in uaa_to_xfi()
1834 return 0; in uaa_to_xfi()
1851 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321); in uaa_to_xfi()
1855 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678); in uaa_to_xfi()
1874 return 0; in uaa_to_xfi()
1900 if (err < 0) in hw_card_start()
1909 if (err < 0) in hw_card_start()
1915 hw->io_base = pci_resource_start(pci, 0); in hw_card_start()
1927 if (hw->irq < 0) { in hw_card_start()
1930 if (err < 0) { in hw_card_start()
1941 return 0; in hw_card_start()
1945 hw->io_base = 0; in hw_card_start()
1956 hw_write_20kx(hw, TRNCTL, 0x00); in hw_card_stop()
1960 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); in hw_card_stop()
1962 return 0; in hw_card_stop()
1967 if (hw->irq >= 0) in hw_card_shutdown()
1977 hw->io_base = 0; in hw_card_shutdown()
1981 return 0; in hw_card_shutdown()
1989 struct dac_conf dac_info = {0}; in hw_card_init()
1990 struct adc_conf adc_info = {0}; in hw_card_init()
1991 struct daio_conf daio_info = {0}; in hw_card_init()
1992 struct trn_conf trn_info = {0}; in hw_card_init()
2001 if (err < 0) in hw_card_init()
2006 if (err < 0) in hw_card_init()
2020 hw_write_20kx(hw, GIE, 0); in hw_card_init()
2022 hw_write_20kx(hw, SRCIP, 0); in hw_card_init()
2028 hw_write_20kx(hw, GPIOCTL, 0x13fe); in hw_card_init()
2031 hw_write_20kx(hw, GPIOCTL, 0x00e6); in hw_card_init()
2034 hw_write_20kx(hw, GPIOCTL, 0x00c2); in hw_card_init()
2037 hw_write_20kx(hw, GPIOCTL, 0x01e6); in hw_card_init()
2043 if (err < 0) in hw_card_init()
2048 if (err < 0) in hw_card_init()
2053 if (err < 0) in hw_card_init()
2058 adc_info.mic20db = 0; in hw_card_init()
2060 if (err < 0) in hw_card_init()
2064 data |= 0x1; /* Enables input from the audio ring */ in hw_card_init()
2067 return 0; in hw_card_init()
2079 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0); in hw_suspend()
2082 return 0; in hw_suspend()
2099 outl(reg, hw->io_base + 0x0); in hw_read_20kx()
2100 value = inl(hw->io_base + 0x4); in hw_read_20kx()
2113 outl(reg, hw->io_base + 0x0); in hw_write_20kx()
2114 outl(data, hw->io_base + 0x4); in hw_write_20kx()
2127 outl(reg, hw->io_base + 0x10); in hw_read_pci()
2128 value = inl(hw->io_base + 0x14); in hw_read_pci()
2141 outl(reg, hw->io_base + 0x10); in hw_write_pci()
2142 outl(data, hw->io_base + 0x14); in hw_write_pci()
2267 return 0; in create_20k1_hw_obj()
2276 return 0; in destroy_20k1_hw_obj()