Lines Matching full:chip
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
86 chip->active_ctrl(chip, 1);
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
188 dev_dbg(chip->card->dev,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
204 struct snd_cs46xx *chip = ac97->private_data;
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
229 chip->active_ctrl(chip, 1);
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
282 chip->active_ctrl(chip, -1);
289 struct snd_cs46xx *chip = ac97->private_data;
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
315 dst = chip->region.idx[bank+1].remap_addr + offset;
382 static int load_firmware(struct snd_cs46xx *chip,
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
478 dst = chip->region.idx[bank+1].remap_addr + offset;
501 static int load_firmware(struct snd_cs46xx *chip)
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
509 if (fw->size != sizeof(*chip->ba1)) {
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
525 size += chip->ba1->memory[i].size;
534 static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip)
538 struct ba1_struct *ba1 = chip->ba1;
541 err = snd_cs46xx_download(chip,
554 * Chip reset
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
602 dev_err(chip->card->dev,
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
746 guard(spinlock_irqsave)(&chip->reg_lock);
747 snd_cs46xx_poke(chip, BA1_PSRC,
749 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
752 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
818 scoped_guard(spinlock_irqsave, &chip->reg_lock) {
819 snd_cs46xx_poke(chip, BA1_CSRC,
821 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
822 snd_cs46xx_poke(chip, BA1_CD,
824 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
848 guard(spinlock_irqsave)(&chip->reg_lock);
849 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
850 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
851 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
852 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
853 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
879 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
882 chip->capt.hw_buf.area + rec->hw_data, bytes);
887 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
888 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
894 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
902 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
904 ptr = snd_cs46xx_peek(chip, BA1_PBA);
912 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
919 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
921 ptr = snd_cs46xx_peek(chip, BA1_PBA);
929 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
930 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
931 return ptr >> chip->capt.shift;
936 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
937 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
938 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
944 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
959 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
963 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
968 scoped_guard(spinlock, &chip->reg_lock) {
972 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
974 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
982 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
986 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
988 scoped_guard(spinlock, &chip->reg_lock) {
990 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
992 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1007 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1010 guard(spinlock)(&chip->reg_lock);
1014 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1016 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1020 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1031 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1037 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1040 dev_err(chip->card->dev,
1049 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1051 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1055 dev_err(chip->card->dev,
1060 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1076 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1086 guard(mutex)(&chip->spos_mutex);
1088 if (_cs46xx_adjust_sample_rate(chip, cpcm, sample_rate))
1095 if (cs46xx_dsp_pcm_channel_set_period(chip, cpcm->pcm_channel, period_size))
1098 dev_dbg(chip->card->dev,
1156 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1178 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1188 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1192 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1224 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1228 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1231 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1233 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1234 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1237 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1238 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1239 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1248 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1253 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1256 if (runtime->dma_area != chip->capt.hw_buf.area)
1258 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1261 if (runtime->dma_area == chip->capt.hw_buf.area)
1274 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1277 if (runtime->dma_area != chip->capt.hw_buf.area)
1286 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1289 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1290 chip->capt.shift = 2;
1291 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1292 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1293 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1294 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1301 struct snd_cs46xx *chip = dev_id;
1304 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1313 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1315 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1320 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1326 if (chip->capt.substream)
1327 snd_pcm_period_elapsed(chip->capt.substream);
1351 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1352 if (chip->playback_pcm->substream)
1353 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1355 if ((status1 & HISR_VC1) && chip->pcm) {
1356 if (chip->capt.substream)
1357 snd_pcm_period_elapsed(chip->capt.substream);
1361 if ((status1 & HISR_MIDI) && chip->rmidi) {
1364 guard(spinlock)(&chip->reg_lock);
1365 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1366 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1367 if ((chip->midcr & MIDCR_RIE) == 0)
1369 snd_rawmidi_receive(chip->midi_input, &c, 1);
1371 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1372 if ((chip->midcr & MIDCR_TIE) == 0)
1374 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1375 chip->midcr &= ~MIDCR_TIE;
1376 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1379 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1385 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1453 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1460 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1472 scoped_guard(mutex, &chip->spos_mutex) {
1481 chip->playback_pcm = cpcm; /* HACK */
1484 if (chip->accept_valid)
1486 chip->active_ctrl(chip, 1);
1512 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1514 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1516 scoped_guard(mutex, &chip->spos_mutex) {
1517 cs46xx_iec958_pre_open(chip);
1528 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1530 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1534 scoped_guard(mutex, &chip->spos_mutex) {
1535 cs46xx_iec958_post_close(chip);
1544 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1546 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1547 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1549 chip->capt.substream = substream;
1552 if (chip->accept_valid)
1555 chip->active_ctrl(chip, 1);
1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1577 scoped_guard(mutex, &chip->spos_mutex) {
1579 cs46xx_dsp_destroy_pcm_channel(chip, cpcm->pcm_channel);
1584 chip->playback_pcm = NULL;
1589 chip->active_ctrl(chip, -1);
1596 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1598 chip->capt.substream = NULL;
1599 snd_dma_free_pages(&chip->capt.hw_buf);
1600 chip->active_ctrl(chip, -1);
1719 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1724 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1728 pcm->private_data = chip;
1736 chip->pcm = pcm;
1739 &chip->pci->dev,
1747 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1752 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1756 pcm->private_data = chip;
1763 chip->pcm_rear = pcm;
1766 &chip->pci->dev,
1772 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1777 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1781 pcm->private_data = chip;
1788 chip->pcm_center_lfe = pcm;
1791 &chip->pci->dev,
1797 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1802 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1806 pcm->private_data = chip;
1813 chip->pcm_iec958 = pcm;
1816 &chip->pci->dev,
1828 struct snd_cs46xx *chip = ac97->private_data;
1830 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1831 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1834 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1835 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1836 chip->eapd_switch = NULL;
1839 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1854 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1856 unsigned int val = snd_cs46xx_peek(chip, reg);
1864 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1868 unsigned int old = snd_cs46xx_peek(chip, reg);
1872 snd_cs46xx_poke(chip, reg, val);
1882 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1884 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1885 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1892 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1895 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1896 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1897 cs46xx_dsp_set_dac_volume(chip,
1909 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1911 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1912 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1918 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1921 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1922 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1923 cs46xx_dsp_set_iec958_volume (chip,
1938 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1942 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1944 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1952 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1957 scoped_guard(mutex, &chip->spos_mutex) {
1958 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1960 cs46xx_dsp_enable_spdif_out(chip);
1962 cs46xx_dsp_disable_spdif_out(chip);
1964 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1968 change = chip->dsp_spos_instance->spdif_status_in;
1970 cs46xx_dsp_enable_spdif_in(chip);
1974 cs46xx_dsp_disable_spdif_in(chip);
1976 res = (change != chip->dsp_spos_instance->spdif_status_in);
1989 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1990 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2003 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2004 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2008 cs46xx_dsp_enable_adc_capture(chip);
2011 cs46xx_dsp_disable_adc_capture(chip);
2020 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2021 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2035 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2036 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2040 cs46xx_dsp_enable_pcm_capture(chip);
2043 cs46xx_dsp_disable_pcm_capture(chip);
2053 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2055 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2071 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2072 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2073 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2077 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2079 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2083 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2084 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2089 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2103 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2104 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2106 guard(mutex)(&chip->spos_mutex);
2118 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2119 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2123 guard(mutex)(&chip->spos_mutex);
2135 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2153 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2154 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2156 guard(mutex)(&chip->spos_mutex);
2168 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2169 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2173 guard(mutex)(&chip->spos_mutex);
2185 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2292 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2294 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2302 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2303 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2381 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2387 ac97.private_data = chip;
2390 if (chip->amplifier_ctrl == amp_voyetra)
2394 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2396 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2397 dev_dbg(chip->card->dev,
2403 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2405 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2406 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2411 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2415 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2417 struct snd_card *card = chip->card;
2429 chip->nr_ac97_codecs = 0;
2430 dev_dbg(chip->card->dev, "detecting primary codec\n");
2431 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2435 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2437 chip->nr_ac97_codecs = 1;
2440 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2442 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2443 chip->nr_ac97_codecs = 2;
2449 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2458 chip->eapd_switch = snd_ctl_find_id_mixer(chip->card,
2462 if (chip->nr_ac97_codecs == 1) {
2463 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2465 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2468 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2473 if (chip->mixer_init) {
2474 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2475 chip->mixer_init(chip);
2480 chip->amplifier_ctrl(chip, 1);
2489 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2491 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2493 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2498 struct snd_cs46xx *chip = substream->rmidi->private_data;
2500 chip->active_ctrl(chip, 1);
2501 guard(spinlock_irq)(&chip->reg_lock);
2502 chip->uartm |= CS46XX_MODE_INPUT;
2503 chip->midcr |= MIDCR_RXE;
2504 chip->midi_input = substream;
2505 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2506 snd_cs46xx_midi_reset(chip);
2508 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2515 struct snd_cs46xx *chip = substream->rmidi->private_data;
2517 scoped_guard(spinlock_irq, &chip->reg_lock) {
2518 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2519 chip->midi_input = NULL;
2520 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2521 snd_cs46xx_midi_reset(chip);
2523 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2525 chip->uartm &= ~CS46XX_MODE_INPUT;
2527 chip->active_ctrl(chip, -1);
2533 struct snd_cs46xx *chip = substream->rmidi->private_data;
2535 chip->active_ctrl(chip, 1);
2537 guard(spinlock_irq)(&chip->reg_lock);
2538 chip->uartm |= CS46XX_MODE_OUTPUT;
2539 chip->midcr |= MIDCR_TXE;
2540 chip->midi_output = substream;
2541 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2542 snd_cs46xx_midi_reset(chip);
2544 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2551 struct snd_cs46xx *chip = substream->rmidi->private_data;
2553 scoped_guard(spinlock_irq, &chip->reg_lock) {
2554 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2555 chip->midi_output = NULL;
2556 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2557 snd_cs46xx_midi_reset(chip);
2559 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2561 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2563 chip->active_ctrl(chip, -1);
2569 struct snd_cs46xx *chip = substream->rmidi->private_data;
2571 guard(spinlock_irqsave)(&chip->reg_lock);
2573 if ((chip->midcr & MIDCR_RIE) == 0) {
2574 chip->midcr |= MIDCR_RIE;
2575 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2578 if (chip->midcr & MIDCR_RIE) {
2579 chip->midcr &= ~MIDCR_RIE;
2580 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2587 struct snd_cs46xx *chip = substream->rmidi->private_data;
2590 guard(spinlock_irqsave)(&chip->reg_lock);
2592 if ((chip->midcr & MIDCR_TIE) == 0) {
2593 chip->midcr |= MIDCR_TIE;
2595 while ((chip->midcr & MIDCR_TIE) &&
2596 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2598 chip->midcr &= ~MIDCR_TIE;
2600 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2603 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2606 if (chip->midcr & MIDCR_TIE) {
2607 chip->midcr &= ~MIDCR_TIE;
2608 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2627 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2632 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2639 rmidi->private_data = chip;
2640 chip->rmidi = rmidi;
2653 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2655 if (snd_BUG_ON(!chip))
2657 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2662 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2664 if (snd_BUG_ON(!chip))
2666 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2671 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2674 if (snd_BUG_ON(!chip))
2677 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2678 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2679 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2706 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2710 chip->gameport = gp = gameport_allocate_port();
2712 dev_err(chip->card->dev,
2718 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2719 gameport_set_dev_parent(gp, &chip->pci->dev);
2720 gameport_set_port_data(gp, chip);
2727 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2728 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2735 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2737 if (chip->gameport) {
2738 gameport_unregister_port(chip->gameport);
2739 chip->gameport = NULL;
2743 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2744 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2768 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2774 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2777 entry->private_data = chip;
2784 cs46xx_dsp_proc_init(card, chip);
2789 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2792 cs46xx_dsp_proc_done(chip);
2797 #define snd_cs46xx_proc_init(card, chip)
2798 #define snd_cs46xx_proc_done(chip)
2804 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2808 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2811 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2813 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2816 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2821 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2822 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2827 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2828 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2833 snd_cs46xx_reset(chip);
2835 snd_cs46xx_proc_stop(chip);
2840 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2846 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2847 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2853 struct snd_cs46xx *chip = card->private_data;
2858 if (chip->active_ctrl)
2859 chip->active_ctrl(chip, 1);
2861 snd_cs46xx_remove_gameport(chip);
2863 if (chip->amplifier_ctrl)
2864 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2866 snd_cs46xx_proc_done(chip);
2868 snd_cs46xx_hw_stop(chip);
2870 if (chip->active_ctrl)
2871 chip->active_ctrl(chip, -chip->amplifier);
2874 if (chip->dsp_spos_instance) {
2875 cs46xx_dsp_spos_destroy(chip);
2876 chip->dsp_spos_instance = NULL;
2879 free_module_desc(chip->modules[idx]);
2881 vfree(chip->ba1);
2886 * initialize chip
2888 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2897 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2898 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2905 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2907 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2909 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2918 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2920 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2923 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2925 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2933 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2935 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2949 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2956 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2957 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2958 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2963 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2973 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2978 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2983 snd_cs46xx_clear_serial_FIFOs(chip);
2988 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
2994 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
2995 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
2996 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3000 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3001 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3002 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3003 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3004 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3019 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3025 dev_err(chip->card->dev,
3027 dev_err(chip->card->dev,
3038 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3045 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3046 dev_dbg(chip->card->dev,
3055 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3057 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3071 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3077 dev_err(chip->card->dev,
3085 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3086 dev_err(chip->card->dev,
3088 dev_err(chip->card->dev,
3090 dev_err(chip->card->dev,
3102 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3109 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3115 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3116 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3125 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3129 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3131 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3133 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3135 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3138 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3141 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3152 snd_cs46xx_reset(chip);
3158 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3160 dev_err(chip->card->dev, "firmware load error [%s]\n",
3164 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3166 dev_err(chip->card->dev, "image download error [%s]\n",
3172 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3175 err = load_firmware(chip);
3180 err = snd_cs46xx_download_image(chip);
3182 dev_err(chip->card->dev, "image download error\n");
3189 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3190 chip->play_ctl = tmp & 0xffff0000;
3191 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3197 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3198 chip->capt.ctl = tmp & 0x0000ffff;
3199 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3203 snd_cs46xx_set_play_sample_rate(chip, 8000);
3204 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3206 snd_cs46xx_proc_start(chip);
3208 cs46xx_enable_stream_irqs(chip);
3212 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3213 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3224 static void amp_none(struct snd_cs46xx *chip, int change)
3229 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3235 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3241 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3244 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3249 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3252 if(chip->nr_ac97_codecs != 2) {
3253 dev_err(chip->card->dev,
3258 modem_power = snd_cs46xx_codec_read (chip,
3263 snd_cs46xx_codec_write(chip,
3270 pin_config = snd_cs46xx_codec_read (chip,
3275 snd_cs46xx_codec_write(chip,
3283 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3287 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3290 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3292 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3294 if ( cs46xx_wait_for_fifo(chip,1) ) {
3295 dev_dbg(chip->card->dev, "FIFO is busy\n");
3310 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3315 if ( cs46xx_wait_for_fifo(chip,200) ) {
3316 dev_dbg(chip->card->dev,
3326 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3331 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3335 cs46xx_wait_for_fifo(chip,200);
3342 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3352 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3358 int old = chip->amplifier;
3362 chip->amplifier += change;
3363 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3366 if (chip->amplifier) {
3374 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3376 if (chip->eapd_switch)
3377 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3378 &chip->eapd_switch->id);
3382 if (chip->amplifier && !old) {
3383 voyetra_setup_eapd_slot(chip);
3388 static void hercules_init(struct snd_cs46xx *chip)
3391 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3392 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3399 static void amp_hercules(struct snd_cs46xx *chip, int change)
3401 int old = chip->amplifier;
3402 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3403 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3405 chip->amplifier += change;
3406 if (chip->amplifier && !old) {
3407 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3409 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3411 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3413 } else if (old && !chip->amplifier) {
3414 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3415 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3416 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3420 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3422 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3425 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3426 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3429 static void hercules_mixer_init (struct snd_cs46xx *chip)
3434 struct snd_card *card = chip->card;
3438 hercules_init(chip);
3440 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3443 if (chip->in_suspend)
3449 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3467 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3469 chip->amplifier += change;
3471 if (chip->amplifier) {
3473 snd_cs46xx_codec_write(chip, 0x4C,
3474 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3475 snd_cs46xx_codec_write(chip, 0x4E,
3476 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3478 snd_cs46xx_codec_write(chip, 0x54,
3479 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3481 snd_cs46xx_codec_write(chip, 0x54,
3482 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3490 * whenever we need to beat on the chip.
3497 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3501 if (!chip->acpi_port)
3504 chip->amplifier += change;
3507 nval = control = inw(chip->acpi_port + 0x10);
3510 if (! chip->amplifier)
3515 outw(nval, chip->acpi_port + 0x10);
3522 static void clkrun_init(struct snd_cs46xx *chip)
3527 chip->acpi_port = 0;
3536 chip->acpi_port = pp << 8;
3681 struct snd_cs46xx *chip = card->private_data;
3685 chip->in_suspend = 1;
3686 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3687 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3689 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3690 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3694 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3696 amp_saved = chip->amplifier;
3698 chip->amplifier_ctrl(chip, -chip->amplifier);
3699 snd_cs46xx_hw_stop(chip);
3701 chip->active_ctrl(chip, -chip->amplifier);
3702 chip->amplifier = amp_saved; /* restore the status */
3709 struct snd_cs46xx *chip = card->private_data;
3716 amp_saved = chip->amplifier;
3717 chip->amplifier = 0;
3718 chip->active_ctrl(chip, 1); /* force to on */
3720 snd_cs46xx_chip_init(chip);
3722 snd_cs46xx_reset(chip);
3724 cs46xx_dsp_resume(chip);
3727 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3729 snd_cs46xx_download_image(chip);
3733 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3734 chip->ac97_general_purpose);
3735 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3736 chip->ac97_powerdown);
3738 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3739 chip->ac97_powerdown);
3743 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3744 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3749 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3750 chip->capt.ctl = tmp & 0x0000ffff;
3751 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3756 snd_cs46xx_set_play_sample_rate(chip, 8000);
3757 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3758 snd_cs46xx_proc_start(chip);
3760 cs46xx_enable_stream_irqs(chip);
3763 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3765 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3766 chip->amplifier = amp_saved;
3767 chip->in_suspend = 0;
3783 struct snd_cs46xx *chip = card->private_data;
3794 spin_lock_init(&chip->reg_lock);
3796 mutex_init(&chip->spos_mutex);
3798 chip->card = card;
3799 chip->pci = pci;
3800 chip->irq = -1;
3805 chip->ba0_addr = pci_resource_start(pci, 0);
3806 chip->ba1_addr = pci_resource_start(pci, 1);
3807 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3808 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3809 dev_err(chip->card->dev,
3811 chip->ba0_addr, chip->ba1_addr);
3815 region = &chip->region.name.ba0;
3817 region->base = chip->ba0_addr;
3820 region = &chip->region.name.data0;
3822 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3825 region = &chip->region.name.data1;
3827 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3830 region = &chip->region.name.pmem;
3832 region->base = chip->ba1_addr + BA1_SP_PMEM;
3835 region = &chip->region.name.reg;
3837 region->base = chip->ba1_addr + BA1_SP_REG;
3846 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3849 chip->amplifier_ctrl = cp->amp;
3850 chip->active_ctrl = cp->active;
3851 chip->mixer_init = cp->mixer_init;
3854 cp->init(chip);
3860 dev_info(chip->card->dev,
3862 chip->amplifier_ctrl = amp_voyetra;
3866 dev_info(chip->card->dev,
3868 chip->active_ctrl = clkrun_hack;
3869 clkrun_init(chip);
3872 if (chip->amplifier_ctrl == NULL)
3873 chip->amplifier_ctrl = amp_none;
3874 if (chip->active_ctrl == NULL)
3875 chip->active_ctrl = amp_none;
3877 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3882 region = &chip->region.idx[idx];
3886 dev_err(chip->card->dev,
3893 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3894 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3897 chip->irq = pci->irq;
3898 card->sync_irq = chip->irq;
3902 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3903 if (!chip->dsp_spos_instance)
3907 err = snd_cs46xx_chip_init(chip);
3911 snd_cs46xx_proc_init(card, chip);
3914 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3916 sizeof(*chip->saved_regs),
3918 if (!chip->saved_regs)
3922 chip->active_ctrl(chip, -1); /* disable CLKRUN */