Lines Matching defs:tmp
79 unsigned short result,tmp;
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
613 unsigned int tmp;
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
969 unsigned int tmp;
972 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
973 tmp &= 0x0000ffff;
974 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
989 unsigned int tmp;
990 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
991 tmp &= 0x0000ffff;
992 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1008 unsigned int tmp;
1014 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1015 tmp &= 0xffff0000;
1016 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1020 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1021 tmp &= 0xffff0000;
1022 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1176 unsigned int tmp;
1224 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1225 tmp &= ~0x000003ff;
1226 tmp |= (4 << cpcm->shift) - 1;
1228 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1234 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1235 tmp &= ~0x000003ff;
1236 tmp |= (4 << cpcm->shift) - 1;
1237 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
2806 unsigned int tmp;
2808 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2809 tmp &= ~0x0000f03f;
2810 tmp |= 0x00000010;
2811 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2813 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2814 tmp &= ~0x0000003f;
2815 tmp |= 0x00000011;
2816 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2821 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2822 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2827 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2828 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2846 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2847 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3115 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3116 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3127 unsigned int tmp;
3131 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3132 tmp &= ~0x0000f03f;
3133 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3135 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3136 tmp &= ~0x0000003f;
3137 tmp |= 0x00000001;
3138 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3143 unsigned int tmp;
3189 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3190 chip->play_ctl = tmp & 0xffff0000;
3191 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3197 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3198 chip->capt.ctl = tmp & 0x0000ffff;
3199 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3232 u32 idx, valid_slots,tmp,powerdown = 0;
3241 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3243 if (!(tmp & CLKCR1_SWCE)) {
3244 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3342 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3714 unsigned int tmp;
3749 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3750 chip->capt.ctl = tmp & 0x0000ffff;
3751 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);