Lines Matching +full:adc +full:- +full:sample +full:- +full:hold +full:- +full:time
1 // SPDX-License-Identifier: GPL-2.0-or-later
29 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
119 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
123 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
129 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
145 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
174 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
175 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
178 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
214 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
218 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
219 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
240 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
254 #define BA0_ACOSV_SLV(x) (1<<((x)-3))
260 #define BA0_ACISV_SLV(x) (1<<((x)-3))
281 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
282 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
289 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
290 #define BA0_AODSD1_NDS(x) (1<<((x)-3))
292 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
293 #define BA0_AODSD2_NDS(x) (1<<((x)-3))
296 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
309 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
310 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
312 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
315 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
316 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
334 #define BA0_PASR 0x0768 /* playback sample rate */
335 #define BA0_CASR 0x076C /* capture sample rate */
337 /* Source Slot Numbers - Playback */
350 /* Source Slot Numbers - Capture */
364 /* Source Slot Numbers - Others */
498 writel(val, chip->ba0 + offset); in snd_cs4281_pokeBA0()
503 return readl(chip->ba0 + offset); in snd_cs4281_peekBA0()
516 struct cs4281 *chip = ac97->private_data; in snd_cs4281_ac97_write()
525 * set DCV - will clear when process completed in snd_cs4281_ac97_write()
526 * reset CRW - Write command in snd_cs4281_ac97_write()
527 * set VFRM - valid frame enabled in snd_cs4281_ac97_write()
528 * set ESYN - ASYNC generation enabled in snd_cs4281_ac97_write()
529 * set RSTN - ARST# inactive, AC97 codec not reset in snd_cs4281_ac97_write()
534 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); in snd_cs4281_ac97_write()
537 * First, we want to wait for a short time. in snd_cs4281_ac97_write()
548 dev_err(chip->card->dev, in snd_cs4281_ac97_write()
555 struct cs4281 *chip = ac97->private_data; in snd_cs4281_ac97_read()
560 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num; in snd_cs4281_ac97_read()
579 * set DCV - will clear when process completed in snd_cs4281_ac97_read()
580 * set CRW - Read command in snd_cs4281_ac97_read()
581 * set VFRM - valid frame enabled in snd_cs4281_ac97_read()
582 * set ESYN - ASYNC generation enabled in snd_cs4281_ac97_read()
583 * set RSTN - ARST# inactive, AC97 codec not reset in snd_cs4281_ac97_read()
598 * First, we want to wait for a short time. in snd_cs4281_ac97_read()
609 dev_err(chip->card->dev, in snd_cs4281_ac97_read()
622 * VSTS - Valid Status in snd_cs4281_ac97_read()
629 dev_err(chip->card->dev, in snd_cs4281_ac97_read()
651 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_trigger()
654 spin_lock(&chip->reg_lock); in snd_cs4281_trigger()
657 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
658 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
661 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
662 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
666 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); in snd_cs4281_trigger()
667 dma->valDMR |= BA0_DMR_DMA; in snd_cs4281_trigger()
668 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
669 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
673 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); in snd_cs4281_trigger()
674 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
675 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
677 if (dma->regFCR != BA0_FCR0) in snd_cs4281_trigger()
678 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
681 spin_unlock(&chip->reg_lock); in snd_cs4281_trigger()
682 return -EINVAL; in snd_cs4281_trigger()
684 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); in snd_cs4281_trigger()
685 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); in snd_cs4281_trigger()
686 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); in snd_cs4281_trigger()
687 spin_unlock(&chip->reg_lock); in snd_cs4281_trigger()
720 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | in snd_cs4281_mode()
722 if (runtime->channels == 1) in snd_cs4281_mode()
723 dma->valDMR |= BA0_DMR_MONO; in snd_cs4281_mode()
724 if (snd_pcm_format_unsigned(runtime->format) > 0) in snd_cs4281_mode()
725 dma->valDMR |= BA0_DMR_USIGN; in snd_cs4281_mode()
726 if (snd_pcm_format_big_endian(runtime->format) > 0) in snd_cs4281_mode()
727 dma->valDMR |= BA0_DMR_BEND; in snd_cs4281_mode()
728 switch (snd_pcm_format_width(runtime->format)) { in snd_cs4281_mode()
729 case 8: dma->valDMR |= BA0_DMR_SIZE8; in snd_cs4281_mode()
730 if (runtime->channels == 1) in snd_cs4281_mode()
731 dma->valDMR |= BA0_DMR_SWAPC; in snd_cs4281_mode()
733 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; in snd_cs4281_mode()
735 dma->frag = 0; /* for workaround */ in snd_cs4281_mode()
736 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; in snd_cs4281_mode()
737 if (runtime->buffer_size != runtime->period_size) in snd_cs4281_mode()
738 dma->valDCR |= BA0_DCR_HTCIE; in snd_cs4281_mode()
740 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); in snd_cs4281_mode()
741 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); in snd_cs4281_mode()
742 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; in snd_cs4281_mode()
743 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | in snd_cs4281_mode()
744 (chip->src_right_play_slot << 8) | in snd_cs4281_mode()
745 (chip->src_left_rec_slot << 16) | in snd_cs4281_mode()
746 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); in snd_cs4281_mode()
750 if (dma->left_slot == chip->src_left_play_slot) { in snd_cs4281_mode()
751 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); in snd_cs4281_mode()
752 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot); in snd_cs4281_mode()
756 if (dma->left_slot == chip->src_left_rec_slot) { in snd_cs4281_mode()
757 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); in snd_cs4281_mode()
758 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot); in snd_cs4281_mode()
764 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
765 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); in snd_cs4281_mode()
767 dma->valFCR = BA0_FCR_LS(dma->left_slot) | in snd_cs4281_mode()
768 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | in snd_cs4281_mode()
770 BA0_FCR_OF(dma->fifo_offset); in snd_cs4281_mode()
771 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); in snd_cs4281_mode()
773 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
774 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); in snd_cs4281_mode()
776 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); in snd_cs4281_mode()
781 struct snd_pcm_runtime *runtime = substream->runtime; in snd_cs4281_playback_prepare()
782 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_playback_prepare()
785 spin_lock_irq(&chip->reg_lock); in snd_cs4281_playback_prepare()
787 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_playback_prepare()
793 struct snd_pcm_runtime *runtime = substream->runtime; in snd_cs4281_capture_prepare()
794 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_capture_prepare()
797 spin_lock_irq(&chip->reg_lock); in snd_cs4281_capture_prepare()
799 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_capture_prepare()
805 struct snd_pcm_runtime *runtime = substream->runtime; in snd_cs4281_pointer()
806 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_pointer()
810 dev_dbg(chip->card->dev, in snd_cs4281_pointer()
812 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, in snd_cs4281_pointer()
815 return runtime->buffer_size - in snd_cs4281_pointer()
816 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; in snd_cs4281_pointer()
872 struct snd_pcm_runtime *runtime = substream->runtime; in snd_cs4281_playback_open()
875 dma = &chip->dma[0]; in snd_cs4281_playback_open()
876 dma->substream = substream; in snd_cs4281_playback_open()
877 dma->left_slot = 0; in snd_cs4281_playback_open()
878 dma->right_slot = 1; in snd_cs4281_playback_open()
879 runtime->private_data = dma; in snd_cs4281_playback_open()
880 runtime->hw = snd_cs4281_playback; in snd_cs4281_playback_open()
882 that although CS4297A rev B reports 18-bit ADC resolution, in snd_cs4281_playback_open()
883 samples are 20-bit */ in snd_cs4281_playback_open()
891 struct snd_pcm_runtime *runtime = substream->runtime; in snd_cs4281_capture_open()
894 dma = &chip->dma[1]; in snd_cs4281_capture_open()
895 dma->substream = substream; in snd_cs4281_capture_open()
896 dma->left_slot = 10; in snd_cs4281_capture_open()
897 dma->right_slot = 11; in snd_cs4281_capture_open()
898 runtime->private_data = dma; in snd_cs4281_capture_open()
899 runtime->hw = snd_cs4281_capture; in snd_cs4281_capture_open()
901 that although CS4297A rev B reports 18-bit ADC resolution, in snd_cs4281_capture_open()
902 samples are 20-bit */ in snd_cs4281_capture_open()
909 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_playback_close()
911 dma->substream = NULL; in snd_cs4281_playback_close()
917 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_capture_close()
919 dma->substream = NULL; in snd_cs4281_capture_close()
944 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); in snd_cs4281_pcm()
951 pcm->private_data = chip; in snd_cs4281_pcm()
952 pcm->info_flags = 0; in snd_cs4281_pcm()
953 strcpy(pcm->name, "CS4281"); in snd_cs4281_pcm()
954 chip->pcm = pcm; in snd_cs4281_pcm()
956 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, in snd_cs4281_pcm()
971 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in snd_cs4281_info_volume()
972 uinfo->count = 2; in snd_cs4281_info_volume()
973 uinfo->value.integer.min = 0; in snd_cs4281_info_volume()
974 uinfo->value.integer.max = CS_VOL_MASK; in snd_cs4281_info_volume()
982 int regL = (kcontrol->private_value >> 16) & 0xffff; in snd_cs4281_get_volume()
983 int regR = kcontrol->private_value & 0xffff; in snd_cs4281_get_volume()
986 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); in snd_cs4281_get_volume()
987 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); in snd_cs4281_get_volume()
989 ucontrol->value.integer.value[0] = volL; in snd_cs4281_get_volume()
990 ucontrol->value.integer.value[1] = volR; in snd_cs4281_get_volume()
999 int regL = (kcontrol->private_value >> 16) & 0xffff; in snd_cs4281_put_volume()
1000 int regR = kcontrol->private_value & 0xffff; in snd_cs4281_put_volume()
1003 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); in snd_cs4281_put_volume()
1004 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); in snd_cs4281_put_volume()
1006 if (ucontrol->value.integer.value[0] != volL) { in snd_cs4281_put_volume()
1007 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); in snd_cs4281_put_volume()
1011 if (ucontrol->value.integer.value[1] != volR) { in snd_cs4281_put_volume()
1012 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); in snd_cs4281_put_volume()
1019 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1045 struct cs4281 *chip = bus->private_data; in snd_cs4281_mixer_free_ac97_bus()
1046 chip->ac97_bus = NULL; in snd_cs4281_mixer_free_ac97_bus()
1051 struct cs4281 *chip = ac97->private_data; in snd_cs4281_mixer_free_ac97()
1052 if (ac97->num) in snd_cs4281_mixer_free_ac97()
1053 chip->ac97_secondary = NULL; in snd_cs4281_mixer_free_ac97()
1055 chip->ac97 = NULL; in snd_cs4281_mixer_free_ac97()
1060 struct snd_card *card = chip->card; in snd_cs4281_mixer()
1068 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus); in snd_cs4281_mixer()
1071 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; in snd_cs4281_mixer()
1076 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97); in snd_cs4281_mixer()
1079 if (chip->dual_codec) { in snd_cs4281_mixer()
1081 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary); in snd_cs4281_mixer()
1102 struct cs4281 *chip = entry->private_data; in snd_cs4281_proc_read()
1105 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); in snd_cs4281_proc_read()
1106 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); in snd_cs4281_proc_read()
1114 struct cs4281 *chip = entry->private_data; in snd_cs4281_BA0_read()
1116 if (copy_to_user_fromio(buf, chip->ba0 + pos, count)) in snd_cs4281_BA0_read()
1117 return -EFAULT; in snd_cs4281_BA0_read()
1126 struct cs4281 *chip = entry->private_data; in snd_cs4281_BA1_read()
1128 if (copy_to_user_fromio(buf, chip->ba1 + pos, count)) in snd_cs4281_BA1_read()
1129 return -EFAULT; in snd_cs4281_BA1_read()
1145 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read); in snd_cs4281_proc_init()
1146 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { in snd_cs4281_proc_init()
1147 entry->content = SNDRV_INFO_CONTENT_DATA; in snd_cs4281_proc_init()
1148 entry->private_data = chip; in snd_cs4281_proc_init()
1149 entry->c.ops = &snd_cs4281_proc_ops_BA0; in snd_cs4281_proc_init()
1150 entry->size = CS4281_BA0_SIZE; in snd_cs4281_proc_init()
1152 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { in snd_cs4281_proc_init()
1153 entry->content = SNDRV_INFO_CONTENT_DATA; in snd_cs4281_proc_init()
1154 entry->private_data = chip; in snd_cs4281_proc_init()
1155 entry->c.ops = &snd_cs4281_proc_ops_BA1; in snd_cs4281_proc_init()
1156 entry->size = CS4281_BA1_SIZE; in snd_cs4281_proc_init()
1206 if (axes[jst] == 0xFFFF) axes[jst] = -1; in snd_cs4281_gameport_cooked_read()
1223 return -1; in snd_cs4281_gameport_open()
1232 chip->gameport = gp = gameport_allocate_port(); in snd_cs4281_create_gameport()
1234 dev_err(chip->card->dev, in snd_cs4281_create_gameport()
1236 return -ENOMEM; in snd_cs4281_create_gameport()
1240 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); in snd_cs4281_create_gameport()
1241 gameport_set_dev_parent(gp, &chip->pci->dev); in snd_cs4281_create_gameport()
1242 gp->open = snd_cs4281_gameport_open; in snd_cs4281_create_gameport()
1243 gp->read = snd_cs4281_gameport_read; in snd_cs4281_create_gameport()
1244 gp->trigger = snd_cs4281_gameport_trigger; in snd_cs4281_create_gameport()
1245 gp->cooked_read = snd_cs4281_gameport_cooked_read; in snd_cs4281_create_gameport()
1258 if (chip->gameport) { in snd_cs4281_free_gameport()
1259 gameport_unregister_port(chip->gameport); in snd_cs4281_free_gameport()
1260 chip->gameport = NULL; in snd_cs4281_free_gameport()
1264 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; } in snd_cs4281_create_gameport()
1270 struct cs4281 *chip = card->private_data; in snd_cs4281_free()
1278 /* Sound System Power Management - Turn Everything OFF */ in snd_cs4281_free()
1288 struct cs4281 *chip = card->private_data; in snd_cs4281_create()
1294 spin_lock_init(&chip->reg_lock); in snd_cs4281_create()
1295 chip->card = card; in snd_cs4281_create()
1296 chip->pci = pci; in snd_cs4281_create()
1297 chip->irq = -1; in snd_cs4281_create()
1300 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec); in snd_cs4281_create()
1303 chip->dual_codec = dual_codec; in snd_cs4281_create()
1308 chip->ba0_addr = pci_resource_start(pci, 0); in snd_cs4281_create()
1309 chip->ba1_addr = pci_resource_start(pci, 1); in snd_cs4281_create()
1311 chip->ba0 = pcim_iomap_table(pci)[0]; in snd_cs4281_create()
1312 chip->ba1 = pcim_iomap_table(pci)[1]; in snd_cs4281_create()
1314 if (devm_request_irq(&pci->dev, pci->irq, snd_cs4281_interrupt, in snd_cs4281_create()
1316 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); in snd_cs4281_create()
1317 return -ENOMEM; in snd_cs4281_create()
1319 chip->irq = pci->irq; in snd_cs4281_create()
1320 card->sync_irq = chip->irq; in snd_cs4281_create()
1321 card->private_free = snd_cs4281_free; in snd_cs4281_create()
1348 dev_err(chip->card->dev, in snd_cs4281_chip_init()
1350 return -EIO; in snd_cs4281_chip_init()
1355 * to 4281h. Allows vendor-defined configuration in snd_cs4281_chip_init()
1361 dev_err(chip->card->dev, in snd_cs4281_chip_init()
1363 return -EIO; in snd_cs4281_chip_init()
1367 dev_err(chip->card->dev, in snd_cs4281_chip_init()
1369 return -EIO; in snd_cs4281_chip_init()
1399 if (chip->dual_codec) in snd_cs4281_chip_init()
1406 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | in snd_cs4281_chip_init()
1430 dev_err(chip->card->dev, "DLLRDY not seen\n"); in snd_cs4281_chip_init()
1431 return -EIO; in snd_cs4281_chip_init()
1456 dev_err(chip->card->dev, in snd_cs4281_chip_init()
1459 return -EIO; in snd_cs4281_chip_init()
1462 if (chip->dual_codec) { in snd_cs4281_chip_init()
1469 dev_info(chip->card->dev, in snd_cs4281_chip_init()
1471 chip->dual_codec = 0; in snd_cs4281_chip_init()
1484 * the codec is pumping ADC data across the AC-link. in snd_cs4281_chip_init()
1498 if (--retry_count > 0) in snd_cs4281_chip_init()
1500 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n"); in snd_cs4281_chip_init()
1501 return -EIO; in snd_cs4281_chip_init()
1515 struct cs4281_dma *dma = &chip->dma[tmp]; in snd_cs4281_chip_init()
1516 dma->regDBA = BA0_DBA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1517 dma->regDCA = BA0_DCA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1518 dma->regDBC = BA0_DBC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1519 dma->regDCC = BA0_DCC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1520 dma->regDMR = BA0_DMR0 + (tmp * 8); in snd_cs4281_chip_init()
1521 dma->regDCR = BA0_DCR0 + (tmp * 8); in snd_cs4281_chip_init()
1522 dma->regHDSR = BA0_HDSR0 + (tmp * 4); in snd_cs4281_chip_init()
1523 dma->regFCR = BA0_FCR0 + (tmp * 4); in snd_cs4281_chip_init()
1524 dma->regFSIC = BA0_FSIC0 + (tmp * 4); in snd_cs4281_chip_init()
1525 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; in snd_cs4281_chip_init()
1526 snd_cs4281_pokeBA0(chip, dma->regFCR, in snd_cs4281_chip_init()
1530 BA0_FCR_OF(dma->fifo_offset)); in snd_cs4281_chip_init()
1533 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ in snd_cs4281_chip_init()
1534 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ in snd_cs4281_chip_init()
1535 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ in snd_cs4281_chip_init()
1536 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ in snd_cs4281_chip_init()
1539 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | in snd_cs4281_chip_init()
1542 BA0_FCR_OF(chip->dma[0].fifo_offset); in snd_cs4281_chip_init()
1543 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); in snd_cs4281_chip_init()
1544 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | in snd_cs4281_chip_init()
1545 (chip->src_right_play_slot << 8) | in snd_cs4281_chip_init()
1546 (chip->src_left_rec_slot << 16) | in snd_cs4281_chip_init()
1547 (chip->src_right_rec_slot << 24)); in snd_cs4281_chip_init()
1573 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); in snd_cs4281_midi_reset()
1575 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_reset()
1580 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_input_open()
1582 spin_lock_irq(&chip->reg_lock); in snd_cs4281_midi_input_open()
1583 chip->midcr |= BA0_MIDCR_RXE; in snd_cs4281_midi_input_open()
1584 chip->midi_input = substream; in snd_cs4281_midi_input_open()
1585 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { in snd_cs4281_midi_input_open()
1588 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_input_open()
1590 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_midi_input_open()
1596 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_input_close()
1598 spin_lock_irq(&chip->reg_lock); in snd_cs4281_midi_input_close()
1599 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); in snd_cs4281_midi_input_close()
1600 chip->midi_input = NULL; in snd_cs4281_midi_input_close()
1601 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { in snd_cs4281_midi_input_close()
1604 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_input_close()
1606 chip->uartm &= ~CS4281_MODE_INPUT; in snd_cs4281_midi_input_close()
1607 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_midi_input_close()
1613 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_output_open()
1615 spin_lock_irq(&chip->reg_lock); in snd_cs4281_midi_output_open()
1616 chip->uartm |= CS4281_MODE_OUTPUT; in snd_cs4281_midi_output_open()
1617 chip->midcr |= BA0_MIDCR_TXE; in snd_cs4281_midi_output_open()
1618 chip->midi_output = substream; in snd_cs4281_midi_output_open()
1619 if (!(chip->uartm & CS4281_MODE_INPUT)) { in snd_cs4281_midi_output_open()
1622 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_output_open()
1624 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_midi_output_open()
1630 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_output_close()
1632 spin_lock_irq(&chip->reg_lock); in snd_cs4281_midi_output_close()
1633 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); in snd_cs4281_midi_output_close()
1634 chip->midi_output = NULL; in snd_cs4281_midi_output_close()
1635 if (!(chip->uartm & CS4281_MODE_INPUT)) { in snd_cs4281_midi_output_close()
1638 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_output_close()
1640 chip->uartm &= ~CS4281_MODE_OUTPUT; in snd_cs4281_midi_output_close()
1641 spin_unlock_irq(&chip->reg_lock); in snd_cs4281_midi_output_close()
1648 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_input_trigger()
1650 spin_lock_irqsave(&chip->reg_lock, flags); in snd_cs4281_midi_input_trigger()
1652 if ((chip->midcr & BA0_MIDCR_RIE) == 0) { in snd_cs4281_midi_input_trigger()
1653 chip->midcr |= BA0_MIDCR_RIE; in snd_cs4281_midi_input_trigger()
1654 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_input_trigger()
1657 if (chip->midcr & BA0_MIDCR_RIE) { in snd_cs4281_midi_input_trigger()
1658 chip->midcr &= ~BA0_MIDCR_RIE; in snd_cs4281_midi_input_trigger()
1659 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_input_trigger()
1662 spin_unlock_irqrestore(&chip->reg_lock, flags); in snd_cs4281_midi_input_trigger()
1668 struct cs4281 *chip = substream->rmidi->private_data; in snd_cs4281_midi_output_trigger()
1671 spin_lock_irqsave(&chip->reg_lock, flags); in snd_cs4281_midi_output_trigger()
1673 if ((chip->midcr & BA0_MIDCR_TIE) == 0) { in snd_cs4281_midi_output_trigger()
1674 chip->midcr |= BA0_MIDCR_TIE; in snd_cs4281_midi_output_trigger()
1676 while ((chip->midcr & BA0_MIDCR_TIE) && in snd_cs4281_midi_output_trigger()
1679 chip->midcr &= ~BA0_MIDCR_TIE; in snd_cs4281_midi_output_trigger()
1684 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_output_trigger()
1687 if (chip->midcr & BA0_MIDCR_TIE) { in snd_cs4281_midi_output_trigger()
1688 chip->midcr &= ~BA0_MIDCR_TIE; in snd_cs4281_midi_output_trigger()
1689 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_midi_output_trigger()
1692 spin_unlock_irqrestore(&chip->reg_lock, flags); in snd_cs4281_midi_output_trigger()
1714 err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi); in snd_cs4281_midi()
1717 strcpy(rmidi->name, "CS4281"); in snd_cs4281_midi()
1720 …rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUP… in snd_cs4281_midi()
1721 rmidi->private_data = chip; in snd_cs4281_midi()
1722 chip->rmidi = rmidi; in snd_cs4281_midi()
1747 cdma = &chip->dma[dma]; in snd_cs4281_interrupt()
1748 spin_lock(&chip->reg_lock); in snd_cs4281_interrupt()
1750 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); in snd_cs4281_interrupt()
1753 cdma->frag++; in snd_cs4281_interrupt()
1754 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { in snd_cs4281_interrupt()
1755 cdma->frag--; in snd_cs4281_interrupt()
1756 chip->spurious_dhtc_irq++; in snd_cs4281_interrupt()
1757 spin_unlock(&chip->reg_lock); in snd_cs4281_interrupt()
1760 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { in snd_cs4281_interrupt()
1761 cdma->frag--; in snd_cs4281_interrupt()
1762 chip->spurious_dtc_irq++; in snd_cs4281_interrupt()
1763 spin_unlock(&chip->reg_lock); in snd_cs4281_interrupt()
1766 spin_unlock(&chip->reg_lock); in snd_cs4281_interrupt()
1767 snd_pcm_period_elapsed(cdma->substream); in snd_cs4281_interrupt()
1771 if ((status & BA0_HISR_MIDI) && chip->rmidi) { in snd_cs4281_interrupt()
1774 spin_lock(&chip->reg_lock); in snd_cs4281_interrupt()
1777 if ((chip->midcr & BA0_MIDCR_RIE) == 0) in snd_cs4281_interrupt()
1779 snd_rawmidi_receive(chip->midi_input, &c, 1); in snd_cs4281_interrupt()
1782 if ((chip->midcr & BA0_MIDCR_TIE) == 0) in snd_cs4281_interrupt()
1784 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { in snd_cs4281_interrupt()
1785 chip->midcr &= ~BA0_MIDCR_TIE; in snd_cs4281_interrupt()
1786 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); in snd_cs4281_interrupt()
1791 spin_unlock(&chip->reg_lock); in snd_cs4281_interrupt()
1808 struct cs4281 *chip = opl3->private_data; in snd_cs4281_opl3_command()
1812 port = chip->ba0 + BA0_B1AP; /* right port */ in snd_cs4281_opl3_command()
1814 port = chip->ba0 + BA0_B0AP; /* left port */ in snd_cs4281_opl3_command()
1816 spin_lock_irqsave(&opl3->reg_lock, flags); in snd_cs4281_opl3_command()
1824 spin_unlock_irqrestore(&opl3->reg_lock, flags); in snd_cs4281_opl3_command()
1837 return -ENODEV; in __snd_cs4281_probe()
1840 return -ENOENT; in __snd_cs4281_probe()
1843 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, in __snd_cs4281_probe()
1847 chip = card->private_data; in __snd_cs4281_probe()
1865 opl3->private_data = chip; in __snd_cs4281_probe()
1866 opl3->command = snd_cs4281_opl3_command; in __snd_cs4281_probe()
1872 strcpy(card->driver, "CS4281"); in __snd_cs4281_probe()
1873 strcpy(card->shortname, "Cirrus Logic CS4281"); in __snd_cs4281_probe()
1874 sprintf(card->longname, "%s at 0x%lx, irq %d", in __snd_cs4281_probe()
1875 card->shortname, in __snd_cs4281_probe()
1876 chip->ba0_addr, in __snd_cs4281_probe()
1877 chip->irq); in __snd_cs4281_probe()
1891 return snd_card_free_on_error(&pci->dev, __snd_cs4281_probe(pci, pci_id)); in snd_cs4281_probe()
1918 struct cs4281 *chip = card->private_data; in cs4281_suspend()
1923 snd_ac97_suspend(chip->ac97); in cs4281_suspend()
1924 snd_ac97_suspend(chip->ac97_secondary); in cs4281_suspend()
1936 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); in cs4281_suspend()
1959 struct cs4281 *chip = card->private_data; in cs4281_resume()
1972 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); in cs4281_resume()
1974 snd_ac97_resume(chip->ac97); in cs4281_resume()
1975 snd_ac97_resume(chip->ac97_secondary); in cs4281_resume()