Lines Matching defs:BA0_CLKCR1

205 #define BA0_CLKCR1		0x0400	/* Clock Control Register 1 */
1273 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1379 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1409 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1411 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1422 		if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1913 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1915 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1932 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1937 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1939 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1950 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1952 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1964 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1966 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);