Lines Matching +full:8 +full:khz
18 * 0.0.8
34 * playback periods_min=2, periods_max=8
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
138 /* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */
140 * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
150 /* 8 general purpose programmable In/Out pins.
151 * GPI [8:0] Read only. Default 0.
152 * GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF)
157 #define CA0106_AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
167 * One list entry is 8 bytes long.
171 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
202 * Start Capture [11:8] (one bit per channel)
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
294 * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)
299 * SPDIF 1 User data [15:8]
343 * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
355 * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
366 * Invert Host to SPDIF Mixer [15:8] (One bit per channel)
375 * SRC Left volume [15:8]
407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
422 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
428 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
436 * I2S Input 0 volume Left [15:8]
554 #define SPI_MASTDA_REG 8
556 #define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */
613 #define SPI_PHASE2_BIT (1<<8)