56 #define C6205_HSR_INTSRC        0x01
57 #define C6205_HSR_INTAVAL       0x02
58 #define C6205_HSR_INTAM         0x04
59 #define C6205_HSR_CFGERR        0x08
60 #define C6205_HSR_EEREAD        0x10
62 #define C6205_HDCR_WARMRESET    0x01
63 #define C6205_HDCR_DSPINT       0x02
64 #define C6205_HDCR_PCIBOOT      0x04
67 #define C6205_DSPP_MAP1         0x400
71  * of DSP memory mapped registers (starting at 0x01800000).
72  * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
75 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
81 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
84 #define HPICL_ADDR      0x01400000L
85 #define HPICH_ADDR      0x01400004L
86 #define HPIAL_ADDR      0x01410000L
87 #define HPIAH_ADDR      0x01410004L
88 #define HPIDIL_ADDR     0x01420000L
89 #define HPIDIH_ADDR     0x01420004L
90 #define HPIDL_ADDR      0x01430000L
91 #define HPIDH_ADDR      0x01430004L
93 #define C6713_EMIF_GCTL         0x01800000
94 #define C6713_EMIF_CE1          0x01800004
95 #define C6713_EMIF_CE0          0x01800008
96 #define C6713_EMIF_CE2          0x01800010
97 #define C6713_EMIF_CE3          0x01800014
98 #define C6713_EMIF_SDRAMCTL     0x01800018
99 #define C6713_EMIF_SDRAMTIMING  0x0180001C
100 #define C6713_EMIF_SDRAMEXT     0x01800020
239 	u16 pending_cache_error = 0;  in control_message()
462 	memset(&ao, 0, sizeof(ao));  in subsys_create_adapter()
487 	phr->error = 0;  in subsys_create_adapter()
503 	boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);  in adapter_delete()
509 	phr->error = 0;  in adapter_delete()
525 	pao->dsp_crashed = 0;  in create_adapter_obj()
527 	for (i = 0; i < HPI_MAX_STREAMS; i++)  in create_adapter_obj()
541 	pao->has_control_cache = 0;  in create_adapter_obj()
555 		memset((void *)phw->p_interface_buffer, 0,  in create_adapter_obj()
595 			memset(p_control_cache_virtual, 0,  in create_adapter_obj()
619 			pao->has_control_cache = 0;  in create_adapter_obj()
629 		memset(&hm, 0, sizeof(hm));  in create_adapter_obj()
630 		/* wAdapterIndex == version == 0 */  in create_adapter_obj()
636 		memset(&hr, 0, sizeof(hr));  in create_adapter_obj()
690 	for (i = 0; i < HPI_MAX_STREAMS; i++)  in delete_adapter_obj()
694 			phw->instream_host_buffer_size[i] = 0;  in delete_adapter_obj()
697 	for (i = 0; i < HPI_MAX_STREAMS; i++)  in delete_adapter_obj()
701 			phw->outstream_host_buffer_size[i] = 0;  in delete_adapter_obj()
712 	u32 hsr = 0;  in adapter_irq_query_and_clear()
732 	u16 err = 0;  in outstream_host_buffer_allocate()
737 	hpi_init_response(phr, phm->object, phm->function, 0);  in outstream_host_buffer_allocate()
770 			phw->outstream_host_buffer_size[phm->obj_index] = 0;  in outstream_host_buffer_allocate()
787 			phw->outstream_host_buffer_size[phm->obj_index] = 0;  in outstream_host_buffer_allocate()
812 		status->samples_processed = 0;  in outstream_host_buffer_allocate()
814 		status->dsp_index = 0;  in outstream_host_buffer_allocate()
817 		status->auxiliary_data_available = 0;  in outstream_host_buffer_allocate()
826 			phw->outstream_host_buffer_size[phm->obj_index] = 0;  in outstream_host_buffer_allocate()
850 			HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);  in outstream_host_buffer_get_info()
869 			phw->outstream_host_buffer_size[phm->obj_index] = 0;  in outstream_host_buffer_free()
882 			HPI_OSTREAM_HOSTBUFFER_FREE, 0);  in outstream_host_buffer_free()
906 	hpi_init_response(phr, phm->object, phm->function, 0);  in outstream_write()
955 		phw->flag_outstream_just_reset[phm->obj_index] = 0;  in outstream_write()
978 	hpi_init_response(phr, phm->object, phm->function, 0);  in outstream_get_info()
1018 	u16 err = 0;  in instream_host_buffer_allocate()
1023 	hpi_init_response(phr, phm->object, phm->function, 0);  in instream_host_buffer_allocate()
1052 			phw->instream_host_buffer_size[phm->obj_index] = 0;  in instream_host_buffer_allocate()
1066 			phw->instream_host_buffer_size[phm->obj_index] = 0;  in instream_host_buffer_allocate()
1089 		status->samples_processed = 0;  in instream_host_buffer_allocate()
1091 		status->dsp_index = 0;  in instream_host_buffer_allocate()
1094 		status->auxiliary_data_available = 0;  in instream_host_buffer_allocate()
1103 			phw->instream_host_buffer_size[phm->obj_index] = 0;  in instream_host_buffer_allocate()
1127 			HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);  in instream_host_buffer_get_info()
1146 			phw->instream_host_buffer_size[phm->obj_index] = 0;  in instream_host_buffer_free()
1159 			HPI_ISTREAM_HOSTBUFFER_FREE, 0);  in instream_host_buffer_free()
1191 	hpi_init_response(phr, phm->object, phm->function, 0);  in instream_read()
1240 	hpi_init_response(phr, phm->object, phm->function, 0);  in instream_get_info()
1263 	int dsp = 0, i = 0;  in adapter_boot_load_dsp()
1264 	u16 err = 0;  in adapter_boot_load_dsp()
1266 	boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);  in adapter_boot_load_dsp()
1273 	case HPI_ADAPTER_FAMILY_ASI(0x5000):  in adapter_boot_load_dsp()
1274 		boot_code_id[0] = boot_code_id[1];  in adapter_boot_load_dsp()
1275 		boot_code_id[1] = 0;  in adapter_boot_load_dsp()
1277 	case HPI_ADAPTER_FAMILY_ASI(0x5300):  in adapter_boot_load_dsp()
1278 	case HPI_ADAPTER_FAMILY_ASI(0x5400):  in adapter_boot_load_dsp()
1279 	case HPI_ADAPTER_FAMILY_ASI(0x6300):  in adapter_boot_load_dsp()
1280 		boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);  in adapter_boot_load_dsp()
1282 	case HPI_ADAPTER_FAMILY_ASI(0x5500):  in adapter_boot_load_dsp()
1283 	case HPI_ADAPTER_FAMILY_ASI(0x5600):  in adapter_boot_load_dsp()
1284 	case HPI_ADAPTER_FAMILY_ASI(0x6500):  in adapter_boot_load_dsp()
1285 		boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);  in adapter_boot_load_dsp()
1287 	case HPI_ADAPTER_FAMILY_ASI(0x8800):  in adapter_boot_load_dsp()
1288 		boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);  in adapter_boot_load_dsp()
1304 	temp |= 0x04;  in adapter_boot_load_dsp()
1328 	temp = 0;  in adapter_boot_load_dsp()
1332 	phw->dsp_page = 0;  in adapter_boot_load_dsp()
1338 	if (boot_code_id[1] != 0) {  in adapter_boot_load_dsp()
1341 		boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202);  in adapter_boot_load_dsp()
1344 		boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);  in adapter_boot_load_dsp()
1345 		/* value of bit 3 is unknown after DSP reset, other bits shoudl be 0 */  in adapter_boot_load_dsp()
1346 		if (0 != (boot_loader_read_mem32(pao, 0,  in adapter_boot_load_dsp()
1352 		boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);  in adapter_boot_load_dsp()
1353 		if (4 != (boot_loader_read_mem32(pao, 0,  in adapter_boot_load_dsp()
1359 	for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {  in adapter_boot_load_dsp()
1361 		if (boot_code_id[dsp] == 0)  in adapter_boot_load_dsp()
1395 			if (length == 0xFFFFFFFF)  in adapter_boot_load_dsp()
1408 			for (i = 0; i < (int)length; i++) {  in adapter_boot_load_dsp()
1413 				if (i % 4 == 0)  in adapter_boot_load_dsp()
1429 			u32 length = 0;  in adapter_boot_load_dsp()
1430 			u32 address = 0;  in adapter_boot_load_dsp()
1431 			u32 type = 0;  in adapter_boot_load_dsp()
1433 			u32 data = 0;  in adapter_boot_load_dsp()
1436 			if (length == 0xFFFFFFFF)  in adapter_boot_load_dsp()
1443 			for (i = 0; i < (int)length; i++) {  in adapter_boot_load_dsp()
1447 					err = 0;  in adapter_boot_load_dsp()
1470 		u32 physicalPC_iaddress_verify = 0;  in adapter_boot_load_dsp()
1481 		host_mailbox_address_on_dsp = 0x80000000;  in adapter_boot_load_dsp()
1484 			boot_loader_write_mem32(pao, 0,  in adapter_boot_load_dsp()
1488 				boot_loader_read_mem32(pao, 0,  in adapter_boot_load_dsp()
1516 	u32 data = 0;  in boot_loader_read_mem32()
1519 	if (dsp_index == 0) {  in boot_loader_read_mem32()
1520 		/* DSP 0 is always C6205 */  in boot_loader_read_mem32()
1521 		if ((address >= 0x01800000) & (address < 0x02000000)) {  in boot_loader_read_mem32()
1524 				(address & 0x007fffff) /  in boot_loader_read_mem32()
1536 			address &= 0x3fffff;	/* address within 4M page */  in boot_loader_read_mem32()
1538 			p_data = pao->pci.ap_mem_base[0] +  in boot_loader_read_mem32()
1545 		boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);  in boot_loader_read_mem32()
1546 		boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);  in boot_loader_read_mem32()
1547 		lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);  in boot_loader_read_mem32()
1548 		data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);  in boot_loader_read_mem32()
1549 		data = (data << 16) | (lsb & 0xFFFF);  in boot_loader_read_mem32()
1559 	/*      u32 dwVerifyData=0; */  in boot_loader_write_mem32()
1561 	if (dsp_index == 0) {  in boot_loader_write_mem32()
1562 		/* DSP 0 is always C6205 */  in boot_loader_write_mem32()
1563 		if ((address >= 0x01800000) & (address < 0x02000000)) {  in boot_loader_write_mem32()
1567 				(address & 0x007fffff) /  in boot_loader_write_mem32()
1579 			address &= 0x3fffff;	/* address within 4M page */  in boot_loader_write_mem32()
1580 			p_data = pao->pci.ap_mem_base[0] +  in boot_loader_write_mem32()
1586 		boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);  in boot_loader_write_mem32()
1587 		boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);  in boot_loader_write_mem32()
1590 		boot_loader_read_mem32(pao, 0, 0);  in boot_loader_write_mem32()
1592 		boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);  in boot_loader_write_mem32()
1593 		boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);  in boot_loader_write_mem32()
1596 		boot_loader_read_mem32(pao, 0, 0);  in boot_loader_write_mem32()
1602 	if (dsp_index == 0) {  in boot_loader_config_emif()
1605 		/* DSP 0 is always C6205 */  in boot_loader_config_emif()
1615 		boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);  in boot_loader_config_emif()
1622 #define RH_OFS 0  in boot_loader_config_emif()
1625 		setting = 0x00000030;  in boot_loader_config_emif()
1626 		boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);  in boot_loader_config_emif()
1628 				0x01800008))  in boot_loader_config_emif()
1632 		/* which occupies D15..0. 6713 starts at 27MHz, so need */  in boot_loader_config_emif()
1639 		boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);  in boot_loader_config_emif()
1641 				0x01800004))  in boot_loader_config_emif()
1645 		/* which occupies D15..0. 6713 starts at 27MHz, so need */  in boot_loader_config_emif()
1651 		boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);  in boot_loader_config_emif()
1653 				0x01800010))  in boot_loader_config_emif()
1662 		boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);  in boot_loader_config_emif()
1664 				0x01800014))  in boot_loader_config_emif()
1669 		boot_loader_write_mem32(pao, dsp_index, 0x01800018,  in boot_loader_config_emif()
1670 			0x07117000);  in boot_loader_config_emif()
1673 		/* EMIF SDRAM timing  (orig = 0x410, emulator = 0x61a) */  in boot_loader_config_emif()
1674 		boot_loader_write_mem32(pao, dsp_index, 0x0180001C,  in boot_loader_config_emif()
1675 			0x00000410);  in boot_loader_config_emif()
1679 		u32 write_data = 0, read_data = 0, i = 0;  in boot_loader_config_emif()
1683 		boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);  in boot_loader_config_emif()
1684 		boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);  in boot_loader_config_emif()
1687 			0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);  in boot_loader_config_emif()
1695 		for (i = 0; i < 32; i++) {  in boot_loader_config_emif()
1696 			boot_loader_write_mem32(pao, 0, HPIAL_ADDR,  in boot_loader_config_emif()
1698 			boot_loader_write_mem32(pao, 0, HPIAH_ADDR,  in boot_loader_config_emif()
1701 				0xFFFF & boot_loader_read_mem32(pao, 0,  in boot_loader_config_emif()
1704 				read_data | ((0xFFFF &  in boot_loader_config_emif()
1705 					boot_loader_read_mem32(pao, 0,  in boot_loader_config_emif()
1724 		boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);  in boot_loader_config_emif()
1727 		boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);  in boot_loader_config_emif()
1729 		boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);  in boot_loader_config_emif()
1731 		boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);  in boot_loader_config_emif()
1736 		boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);  in boot_loader_config_emif()
1738 		boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);  in boot_loader_config_emif()
1740 		/* FSX0 <- '0' (GPO3) */  in boot_loader_config_emif()
1741 		boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);  in boot_loader_config_emif()
1745 		boot_loader_write_mem32(pao, 0, 0x01800004,	/* CE1 */  in boot_loader_config_emif()
1754 		if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)  in boot_loader_config_emif()
1755 			!= 0x0001) {  in boot_loader_config_emif()
1761 			0x000034A8);  in boot_loader_config_emif()
1772 		   2..0         Rd hold  in boot_loader_config_emif()
1775 			0x00000030);  in boot_loader_config_emif()
1778 		   0x00  in boot_loader_config_emif()
1791 		   4            TRRD = 2cycle      = 0b  (tRRD = 14ns)  in boot_loader_config_emif()
1797 			0x001BDF29);  in boot_loader_config_emif()
1800 		   31           -       0b       -  in boot_loader_config_emif()
1814 		   11..0        -       0000b 0000b 0000b  in boot_loader_config_emif()
1817 			0x47116000);  in boot_loader_config_emif()
1820 		   Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A  in boot_loader_config_emif()
1823 			C6713_EMIF_SDRAMTIMING, 0x00000410);  in boot_loader_config_emif()
1830 	return 0;  in boot_loader_config_emif()
1836 	u32 i = 0, j = 0;  in boot_loader_test_memory()
1837 	u32 test_addr = 0;  in boot_loader_test_memory()
1838 	u32 test_data = 0, data = 0;  in boot_loader_test_memory()
1844 	/*for(i=0; i<dwLength; i++) */  in boot_loader_test_memory()
1845 	i = 0;  in boot_loader_test_memory()
1848 		test_data = 0x00000001;  in boot_loader_test_memory()
1849 		for (j = 0; j < 32; j++) {  in boot_loader_test_memory()
1868 	for (i = 0; i < 100; i++) {  in boot_loader_test_memory()
1870 		test_data = 0xA5A55A5A;  in boot_loader_test_memory()
1872 		boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);  in boot_loader_test_memory()
1882 		boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);  in boot_loader_test_memory()
1886 	for (i = 0; i < length; i++) {  in boot_loader_test_memory()
1888 		boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);  in boot_loader_test_memory()
1890 	return 0;  in boot_loader_test_memory()
1896 	int err = 0;  in boot_loader_test_internal_memory()
1897 	if (dsp_index == 0) {  in boot_loader_test_internal_memory()
1898 		/* DSP 0 is a C6205 */  in boot_loader_test_internal_memory()
1900 		err = boot_loader_test_memory(pao, dsp_index, 0x00000000,  in boot_loader_test_internal_memory()
1901 			0x10000);  in boot_loader_test_internal_memory()
1905 				0x80000000, 0x10000);  in boot_loader_test_internal_memory()
1909 		err = boot_loader_test_memory(pao, dsp_index, 0x00000000,  in boot_loader_test_internal_memory()
1910 			0x30000);  in boot_loader_test_internal_memory()
1914 				0x00030000, 0x10000);  in boot_loader_test_internal_memory()
1920 		return 0;  in boot_loader_test_internal_memory()
1926 	u32 dRAM_start_address = 0;  in boot_loader_test_external_memory()
1927 	u32 dRAM_size = 0;  in boot_loader_test_external_memory()
1929 	if (dsp_index == 0) {  in boot_loader_test_external_memory()
1931 		if (pao->pci.pci_dev->subsystem_device == 0x5000) {  in boot_loader_test_external_memory()
1932 			/* DSP 0 is always C6205 */  in boot_loader_test_external_memory()
1933 			dRAM_start_address = 0x00400000;  in boot_loader_test_external_memory()
1934 			dRAM_size = 0x200000;  in boot_loader_test_external_memory()
1937 			return 0;  in boot_loader_test_external_memory()
1940 		dRAM_start_address = 0x80000000;  in boot_loader_test_external_memory()
1941 		dRAM_size = 0x200000;  in boot_loader_test_external_memory()
1948 	return 0;  in boot_loader_test_external_memory()
1953 	u32 data = 0;  in boot_loader_test_pld()
1954 	if (dsp_index == 0) {  in boot_loader_test_pld()
1956 		if (pao->pci.pci_dev->subsystem_device == 0x5000) {  in boot_loader_test_pld()
1957 			/* PLD is located at CE3=0x03000000 */  in boot_loader_test_pld()
1959 				0x03000008);  in boot_loader_test_pld()
1960 			if ((data & 0xF) != 0x5)  in boot_loader_test_pld()
1963 				0x0300000C);  in boot_loader_test_pld()
1964 			if ((data & 0xF) != 0xA)  in boot_loader_test_pld()
1969 		if (pao->pci.pci_dev->subsystem_device == 0x8700) {  in boot_loader_test_pld()
1970 			/* PLD is located at CE1=0x90000000 */  in boot_loader_test_pld()
1972 				0x90000010);  in boot_loader_test_pld()
1973 			if ((data & 0xFF) != 0xAA)  in boot_loader_test_pld()
1976 			boot_loader_write_mem32(pao, dsp_index, 0x90000000,  in boot_loader_test_pld()
1977 				0x02);  in boot_loader_test_pld()
1980 	return 0;  in boot_loader_test_pld()
1990 	u32 data_transferred = 0;  in hpi6205_transfer_data()
1991 	u16 err = 0;  in hpi6205_transfer_data()
2011 			memcpy((void *)&interface->u.b_data[0],  in hpi6205_transfer_data()
2034 				(void *)&interface->u.b_data[0], this_copy);  in hpi6205_transfer_data()
2090 	u16 err = 0;  in message_response_sequence()
2100 		return 0;  in message_response_sequence()
2172 	u16 err = 0;  in hw_message()
2194 		pao->dsp_crashed = 0;  in hw_message()
2196 	if (phr->error != 0)	/* something failed in the DSP */  in hw_message()