Lines Matching +full:0 +full:x7f00
22 #define SRAM_BANK_SIZE 0x8000
23 #define SRAM_CNTL_START 0x7F00
24 #define SMA_STRUCT_START 0x7F40
26 #define DSP_BASE_ADDR 0x4000
27 #define DSP_BANK_BASE 0x4000
29 #define AGND 0x01
30 #define SIGNAL 0x02
32 #define EXT_DSP_BIT_DCAL 0x0001
33 #define EXT_DSP_BIT_MIDI_CON 0x0002
35 #define BUFFSIZE 0x8000
36 #define HOSTQ_SIZE 0x40
38 #define DAP_BUFF_SIZE 0x2400
40 #define DAPQ_STRUCT_SIZE 0x10
41 #define DARQ_STRUCT_SIZE 0x10
42 #define DAPQ_BUFF_SIZE (3 * 0x10)
43 #define DARQ_BUFF_SIZE (3 * 0x10)
44 #define MODQ_BUFF_SIZE 0x400
46 #define DAPQ_DATA_BUFF 0x6C00
47 #define DARQ_DATA_BUFF 0x6C30
48 #define MODQ_DATA_BUFF 0x6C60
49 #define MIDQ_DATA_BUFF 0x7060
52 #define DARQ_OFFSET (SRAM_CNTL_START + 0x08)
53 #define MODQ_OFFSET (SRAM_CNTL_START + 0x10)
54 #define MIDQ_OFFSET (SRAM_CNTL_START + 0x18)
55 #define DSPQ_OFFSET (SRAM_CNTL_START + 0x20)
57 #define HP_ICR 0x00
58 #define HP_CVR 0x01
59 #define HP_ISR 0x02
60 #define HP_IVR 0x03
61 #define HP_NU 0x04
62 #define HP_INFO 0x04
63 #define HP_TXH 0x05
64 #define HP_RXH 0x05
65 #define HP_TXM 0x06
66 #define HP_RXM 0x06
67 #define HP_TXL 0x07
68 #define HP_RXL 0x07
70 #define HP_ICR_DEF 0x00
71 #define HP_CVR_DEF 0x12
72 #define HP_ISR_DEF 0x06
73 #define HP_IVR_DEF 0x0f
74 #define HP_NU_DEF 0x00
76 #define HP_IRQM 0x09
78 #define HPR_BLRC 0x08
79 #define HPR_SPR1 0x09
80 #define HPR_SPR2 0x0A
81 #define HPR_TCL0 0x0B
82 #define HPR_TCL1 0x0C
83 #define HPR_TCL2 0x0D
84 #define HPR_TCL3 0x0E
85 #define HPR_TCL4 0x0F
87 #define HPICR_INIT 0x80
88 #define HPICR_HM1 0x40
89 #define HPICR_HM0 0x20
90 #define HPICR_HF1 0x10
91 #define HPICR_HF0 0x08
92 #define HPICR_TREQ 0x02
93 #define HPICR_RREQ 0x01
95 #define HPCVR_HC 0x80
97 #define HPISR_HREQ 0x80
98 #define HPISR_DMA 0x40
99 #define HPISR_HF3 0x10
100 #define HPISR_HF2 0x08
101 #define HPISR_TRDY 0x04
102 #define HPISR_TXDE 0x02
103 #define HPISR_RXDF 0x01
105 #define HPIO_290 0
114 #define HPMEM_NONE 0
123 #define HPIRQ_NONE 0
132 #define HIMT_PLAY_DONE 0x00
133 #define HIMT_RECORD_DONE 0x01
134 #define HIMT_MIDI_EOS 0x02
135 #define HIMT_MIDI_OUT 0x03
137 #define HIMT_MIDI_IN_UCHAR 0x0E
138 #define HIMT_DSP 0x0F
140 #define HDEX_BASE 0x92
141 #define HDEX_PLAY_START (0 + HDEX_BASE)
160 #define HDEXAR_SET_ANA_IN 0
169 #define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF))
171 #define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF))
188 #define JQS_wStart 0x00
189 #define JQS_wSize 0x02
190 #define JQS_wHead 0x04
191 #define JQS_wTail 0x06
192 #define JQS__size 0x08
195 #define DAQDS_wStart 0x00
196 #define DAQDS_wSize 0x02
197 #define DAQDS_wFormat 0x04
198 #define DAQDS_wSampleSize 0x06
199 #define DAQDS_wChannels 0x08
200 #define DAQDS_wSampleRate 0x0A
201 #define DAQDS_wIntMsg 0x0C
202 #define DAQDS_wFlags 0x0E
203 #define DAQDS__size 0x10
240 #define F_RESETTING 0