Lines Matching +full:start +full:- +full:up
1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio stream operations
26 * +--+-------+
28 * +--+----+--+
32 * +--+----+--+
34 * +--+----+--+
39 * +--+----+--+
41 * +--+----+--+
45 * +--+----+--+
47 * +----------+
51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus
58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->channels,
60 rate = runtime->rate,
61 bits_per_sample = runtime->sample_bits,
75 if (value >= bus->sdo_limit)
85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to initialize
97 azx_dev->bus = bus;
99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
106 list_add_tail(&azx_dev->list, &bus->stream_list);
108 if (bus->spbcap) {
109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
118 if (bus->drsmcap)
119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
128 * Start a stream, set start_wallclk and set the running flag.
132 struct hdac_bus *bus = azx_dev->bus;
137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
141 1 << azx_dev->index,
142 1 << azx_dev->index);
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword)
159 azx_dev->running = true;
164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165 * @azx_dev: HD-audio core stream to stop
172 if (azx_dev->stripe)
174 azx_dev->running = false;
178 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop
185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
194 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus
201 list_for_each_entry(stream, &bus->stream_list, list)
207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208 * @bus: HD-audio core bus
213 if (bus->chip_init) {
221 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset
238 if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 udelay(azx_dev->bus->dma_stop_delay);
246 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0;
253 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PCM or code-loading.
259 struct hdac_bus *bus = azx_dev->bus;
265 if (azx_dev->substream)
266 runtime = azx_dev->substream->runtime;
274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop)
280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
294 upper_32_bits(azx_dev->bdl.addr));
297 if (bus->use_posbuf && bus->posbuf.addr) {
300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */
311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n",
313 azx_dev->fifo_size = reg;
320 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runtime, 64);
324 azx_dev->delay_negative_threshold = 0;
328 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->rate) * 1000);
336 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up
344 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0;
351 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus
358 * beforehand. Also, when bus->reverse_assign flag is set, the last free
367 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | (substream->stream + 1);
370 if (substream->pcm)
371 key |= (substream->pcm->device << 16);
373 guard(spinlock_irq)(&bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != substream->stream)
377 if (azx_dev->opened)
379 if (azx_dev->assigned_key == key) {
383 if (!res || bus->reverse_assign)
387 res->opened = 1;
388 res->running = 0;
389 res->assigned_key = key;
390 res->substream = substream;
397 * snd_hdac_stream_release_locked - release the assigned stream
398 * @azx_dev: HD-audio core stream to release
401 * The bus->reg_lock needs to be taken at a higher level
405 azx_dev->opened = 0;
406 azx_dev->running = 0;
407 azx_dev->substream = NULL;
412 * snd_hdac_stream_release - release the assigned stream
413 * @azx_dev: HD-audio core stream to release
419 struct hdac_bus *bus = azx_dev->bus;
421 guard(spinlock_irq)(&bus->reg_lock);
427 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
430 * @bus: HD-audio core bus
439 list_for_each_entry(s, &bus->stream_list, list) {
440 if (s->direction == dir && s->stream_tag == stream_tag)
449 * set up a BDL entry
462 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
463 return -EINVAL;
472 if (bus->align_bdle_4k) {
473 u32 remain = 0x1000 - (ofs & 0xfff);
482 size -= chunk;
485 azx_dev->frags++;
493 * snd_hdac_stream_setup_bdle - set up BDL entries
494 * @azx_dev: HD-audio core stream to set up
498 * Set up the buffer descriptor table of the given stream based on the
504 struct hdac_bus *bus = azx_dev->bus;
513 period_bytes = azx_dev->period_bytes;
514 periods = azx_dev->bufsize / period_bytes;
517 bdl = (__le32 *)azx_dev->bdl.area;
519 azx_dev->frags = 0;
521 pos_adj = bus->bdl_pos_adj;
522 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
524 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
531 dev_warn(bus->dev, "Too big adjustment %d\n",
544 if (i == periods - 1 && pos_adj)
546 &bdl, ofs, period_bytes - pos_adj, 0);
550 !azx_dev->no_period_wakeup);
557 dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
558 azx_dev->bufsize, period_bytes);
559 return -EINVAL;
563 * snd_hdac_stream_setup_periods - set up BDL entries
564 * @azx_dev: HD-audio core stream to set up
566 * Set up the buffer descriptor table of the given stream based on the
571 struct snd_pcm_substream *substream = azx_dev->substream;
572 struct snd_compr_stream *cstream = azx_dev->cstream;
577 runtime = substream->runtime;
583 return -EINVAL;
591 * snd_hdac_stream_set_params - set stream parameters
592 * @azx_dev: HD-audio core stream for which parameters are to be set
595 * Setup the HD-audio core stream parameters from substream of the stream
601 struct snd_pcm_substream *substream = azx_dev->substream;
602 struct snd_compr_stream *cstream = azx_dev->cstream;
610 no_period_wakeup = substream->runtime->no_period_wakeup;
612 bufsize = cstream->runtime->buffer_size;
613 period_bytes = cstream->runtime->fragment_size;
616 return -EINVAL;
619 if (bufsize != azx_dev->bufsize ||
620 period_bytes != azx_dev->period_bytes ||
621 format_val != azx_dev->format_val ||
622 no_period_wakeup != azx_dev->no_period_wakeup) {
623 azx_dev->bufsize = bufsize;
624 azx_dev->period_bytes = period_bytes;
625 azx_dev->format_val = format_val;
626 azx_dev->no_period_wakeup = no_period_wakeup;
639 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
645 struct timecounter *tc = &azx_dev->tc;
646 struct cyclecounter *cc = &azx_dev->cc;
649 cc->read = azx_cc_read;
650 cc->mask = CLOCKSOURCE_MASK(32);
656 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
666 tc->cycle_last = last;
671 * snd_hdac_stream_timecounter_init - initialize time counter
672 * @azx_dev: HD-audio core stream (master stream)
673 * @streams: bit flags of streams to set up
674 * @start: true for PCM trigger start, false for other cases
682 unsigned int streams, bool start)
684 struct hdac_bus *bus = azx_dev->bus;
685 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
690 if (!start)
693 list_for_each_entry(s, &bus->stream_list, list) {
694 if ((streams & (1 << s->index))) {
698 cycle_last = s->tc.cycle_last;
704 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
705 runtime->trigger_tstamp_latched = true;
710 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
711 * @azx_dev: HD-audio core stream (master stream)
719 struct hdac_bus *bus = azx_dev->bus;
734 * snd_hdac_stream_sync - sync with start/stop trigger operation
735 * @azx_dev: HD-audio core stream (master stream)
736 * @start: true = start, false = stop
739 * For @start = true, wait until all FIFOs get ready.
740 * For @start = false, wait until all RUN bits are cleared.
742 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
745 struct hdac_bus *bus = azx_dev->bus;
749 for (timeout = 5000; timeout; timeout--) {
751 list_for_each_entry(s, &bus->stream_list, list) {
752 if (!(streams & (1 << s->index)))
755 if (start) {
782 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
783 * @bus: HD-audio core bus
792 if (!bus->spbcap) {
793 dev_err(bus->dev, "Address of SPB capability is NULL\n");
800 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
802 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
807 * snd_hdac_stream_set_spib - sets the spib value of a stream
808 * @bus: HD-audio core bus
815 if (!bus->spbcap) {
816 dev_err(bus->dev, "Address of SPB capability is NULL\n");
817 return -EINVAL;
820 writel(value, azx_dev->spib_addr);
827 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
828 * @bus: HD-audio core bus
837 if (!bus->drsmcap) {
838 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
845 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
847 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
852 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
853 * @azx_dev: HD-audio core stream to await RSM for
855 * Returns 0 on success and -ETIMEDOUT upon a timeout.
859 struct hdac_bus *bus = azx_dev->bus;
863 mask = 1 << azx_dev->index;
866 bus->drsmcap + AZX_REG_DRSM_CTL);
868 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
874 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
875 * @bus: HD-audio core bus
882 if (!bus->drsmcap) {
883 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
884 return -EINVAL;
887 writel(value, azx_dev->dpibr_addr);
894 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
908 * snd_hdac_dsp_prepare - prepare for DSP loading
909 * @azx_dev: HD-audio core stream used for DSP loading
910 * @format: HD-audio stream format
914 * Allocate the buffer for the given size and set up the given stream for
920 struct hdac_bus *bus = azx_dev->bus;
924 scoped_guard(spinlock_irq, &bus->reg_lock) {
925 if (azx_dev->running || azx_dev->locked)
926 return -EBUSY;
927 azx_dev->locked = true;
930 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
935 azx_dev->substream = NULL;
936 azx_dev->bufsize = byte_size;
938 azx_dev->period_bytes = byte_size / 2;
939 azx_dev->format_val = format;
940 azx_dev->no_period_wakeup = 1;
949 return azx_dev->stream_tag;
954 scoped_guard(spinlock_irq, &bus->reg_lock) {
955 azx_dev->locked = false;
962 * snd_hdac_dsp_trigger - start / stop DSP loading
963 * @azx_dev: HD-audio core stream used for DSP loading
964 * @start: trigger start or stop
966 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
968 if (start)
976 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
977 * @azx_dev: HD-audio core stream used for DSP loading
983 struct hdac_bus *bus = azx_dev->bus;
985 if (!dmab->area || !azx_dev->locked)
993 azx_dev->bufsize = 0;
994 azx_dev->period_bytes = 0;
995 azx_dev->format_val = 0;
998 dmab->area = NULL;
1000 guard(spinlock_irq)(&bus->reg_lock);
1001 azx_dev->locked = false;