Lines Matching full:bus
15 static void azx_clear_corbrp(struct hdac_bus *bus)
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
28 snd_hdac_chip_writew(bus, CORBRP, 0);
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
41 * @bus: HD-audio core bus
43 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
45 WARN_ON_ONCE(!bus->rb.area);
47 guard(spinlock_irq)(&bus->reg_lock);
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
57 snd_hdac_chip_writew(bus, CORBWP, 0);
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
65 if (!bus->use_pio_for_commands)
66 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
69 bus->rirb.addr = bus->rb.addr + 2048;
70 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
71 bus->rirb.wp = bus->rirb.rp = 0;
72 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
73 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
74 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
77 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
79 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
81 snd_hdac_chip_writew(bus, RINTCNT, 1);
83 if (bus->not_use_interrupts)
84 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
86 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
88 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
93 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
98 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
103 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
110 * @bus: HD-audio core bus
112 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
114 scoped_guard(spinlock_irq, &bus->reg_lock) {
116 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
117 snd_hdac_chip_writeb(bus, CORBCTL, 0);
120 hdac_wait_for_cmd_dmas(bus);
122 guard(spinlock_irq)(&bus->reg_lock);
124 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
138 static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus,
145 if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) {
147 bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
153 dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n",
154 snd_hdac_chip_readw(bus, IRS));
156 bus->rirb.res[addr] = -1;
163 * @bus: HD-audio core bus
168 static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val)
173 guard(spinlock_irq)(&bus->reg_lock);
177 if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) {
179 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID);
180 snd_hdac_chip_writel(bus, IC, val);
182 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY);
184 return snd_hdac_bus_wait_for_pio_response(bus, addr);
189 dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n",
190 snd_hdac_chip_readw(bus, IRS), val);
197 * @bus: HD-audio core bus
203 static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus,
207 *res = bus->rirb.res[addr];
214 * @bus: HD-audio core bus
219 static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val)
224 guard(spinlock_irq)(&bus->reg_lock);
226 bus->last_cmd[azx_command_addr(val)] = val;
229 wp = snd_hdac_chip_readw(bus, CORBWP);
237 rp = snd_hdac_chip_readw(bus, CORBRP);
243 bus->rirb.cmds[addr]++;
244 bus->corb.buf[wp] = cpu_to_le32(val);
245 snd_hdac_chip_writew(bus, CORBWP, wp);
254 * @bus: HD-audio core bus
257 * The caller needs bus->reg_lock spinlock before calling this.
259 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
265 wp = snd_hdac_chip_readw(bus, RIRBWP);
271 if (wp == bus->rirb.wp)
273 bus->rirb.wp = wp;
275 while (bus->rirb.rp != wp) {
276 bus->rirb.rp++;
277 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
279 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
280 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
281 res = le32_to_cpu(bus->rirb.buf[rp]);
284 dev_err(bus->dev,
286 res, res_ex, bus->rirb.rp, wp);
289 snd_hdac_bus_queue_event(bus, res, res_ex);
290 else if (bus->rirb.cmds[addr]) {
291 bus->rirb.res[addr] = res;
292 bus->rirb.cmds[addr]--;
293 if (!bus->rirb.cmds[addr] &&
294 waitqueue_active(&bus->rirb_wq))
295 wake_up(&bus->rirb_wq);
297 dev_err_ratelimited(bus->dev,
299 res, res_ex, bus->last_cmd[addr]);
307 * @bus: HD-audio core bus
313 static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus,
325 scoped_guard(spinlock_irq, &bus->reg_lock) {
326 if (!bus->polling_mode)
327 prepare_to_wait(&bus->rirb_wq, &wait,
329 if (bus->polling_mode)
330 snd_hdac_bus_update_rirb(bus);
331 if (!bus->rirb.cmds[addr]) {
333 *res = bus->rirb.res[addr]; /* the last value */
334 if (!bus->polling_mode)
335 finish_wait(&bus->rirb_wq, &wait);
342 if (!bus->polling_mode) {
344 } else if (bus->needs_damn_long_delay ||
347 dev_dbg_ratelimited(bus->dev,
349 bus->last_cmd[addr]);
359 if (!bus->polling_mode)
360 finish_wait(&bus->rirb_wq, &wait);
367 * @bus: HD-audio core bus
372 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
374 if (bus->use_pio_for_commands)
375 return snd_hdac_bus_send_cmd_pio(bus, val);
377 return snd_hdac_bus_send_cmd_corb(bus, val);
383 * @bus: HD-audio core bus
389 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
392 if (bus->use_pio_for_commands)
393 return snd_hdac_bus_get_response_pio(bus, addr, res);
395 return snd_hdac_bus_get_response_rirb(bus, addr, res);
402 * @bus: the pointer to bus object
406 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
412 offset = snd_hdac_chip_readw(bus, LLCH);
416 cur_cap = _snd_hdac_chip_readl(bus, offset);
418 dev_dbg(bus->dev, "Capability version: 0x%x\n",
421 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
425 dev_dbg(bus->dev, "Invalid capability reg read\n");
431 dev_dbg(bus->dev, "Found ML capability\n");
432 bus->mlcap = bus->remap_addr + offset;
436 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
437 bus->gtscap = bus->remap_addr + offset;
442 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
443 bus->ppcap = bus->remap_addr + offset;
448 dev_dbg(bus->dev, "Found SPB capability\n");
449 bus->spbcap = bus->remap_addr + offset;
454 dev_dbg(bus->dev, "Found DRSM capability\n");
455 bus->drsmcap = bus->remap_addr + offset;
459 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
467 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
486 * @bus: HD-audio core bus
490 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
495 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
498 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
506 * @bus: HD-audio core bus
510 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
514 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
517 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
523 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
529 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
530 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
533 snd_hdac_bus_enter_link_reset(bus);
541 snd_hdac_bus_exit_link_reset(bus);
548 if (!snd_hdac_chip_readb(bus, GCTL)) {
549 dev_dbg(bus->dev, "controller not ready!\n");
554 if (!bus->codec_mask) {
555 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
556 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
564 static void azx_int_enable(struct hdac_bus *bus)
567 snd_hdac_chip_updatel(bus, INTCTL,
573 static void azx_int_disable(struct hdac_bus *bus)
578 list_for_each_entry(azx_dev, &bus->stream_list, list)
582 snd_hdac_chip_writel(bus, INTCTL, 0);
586 static void azx_int_clear(struct hdac_bus *bus)
591 list_for_each_entry(azx_dev, &bus->stream_list, list)
595 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
598 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
601 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
606 * @bus: HD-audio core bus
609 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
611 if (bus->chip_init)
615 snd_hdac_bus_reset_link(bus, full_reset);
618 azx_int_clear(bus);
621 snd_hdac_bus_init_cmd_io(bus);
624 azx_int_enable(bus);
627 if (bus->use_posbuf && bus->posbuf.addr) {
628 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
629 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
632 bus->chip_init = true;
640 * @bus: HD-audio core bus
642 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
644 if (!bus->chip_init)
648 azx_int_disable(bus);
649 azx_int_clear(bus);
652 snd_hdac_bus_stop_cmd_io(bus);
655 if (bus->posbuf.addr) {
656 snd_hdac_chip_writel(bus, DPLBASE, 0);
657 snd_hdac_chip_writel(bus, DPUBASE, 0);
660 bus->chip_init = false;
666 * @bus: HD-audio core bus
672 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
680 list_for_each_entry(azx_dev, &bus->stream_list, list) {
689 ack(bus, azx_dev);
698 * @bus: HD-audio core bus
703 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
707 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
710 list_for_each_entry(s, &bus->stream_list, list) {
712 err = snd_dma_alloc_pages(dma_type, bus->dev,
722 err = snd_dma_alloc_pages(dma_type, bus->dev,
723 num_streams * 8, &bus->posbuf);
726 list_for_each_entry(s, &bus->stream_list, list)
727 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
730 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
736 * @bus: HD-audio core bus
738 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
742 list_for_each_entry(s, &bus->stream_list, list) {
747 if (bus->rb.area)
748 snd_dma_free_pages(&bus->rb);
749 if (bus->posbuf.area)
750 snd_dma_free_pages(&bus->posbuf);
762 set_bit(codec->addr, &codec->bus->codec_powered);
764 clear_bit(codec->addr, &codec->bus->codec_powered);