Lines Matching full:hda
77 /* Defines for Nvidia HDA support */
84 /* Defines for Intel SCH HDA snoop control */
155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
210 MODULE_DESCRIPTION("Intel HDA driver");
340 [AZX_DRIVER_ICH] = "HDA Intel",
341 [AZX_DRIVER_PCH] = "HDA Intel PCH",
342 [AZX_DRIVER_SCH] = "HDA Intel MID",
343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
345 [AZX_DRIVER_ATI] = "HDA ATI SB",
346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
350 [AZX_DRIVER_SIS] = "HDA SIS966",
351 [AZX_DRIVER_ULI] = "HDA ULI M5461",
352 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
353 [AZX_DRIVER_TERA] = "HDA Teradici",
354 [AZX_DRIVER_CTX] = "HDA Creative",
355 [AZX_DRIVER_CTHDA] = "HDA Creative",
356 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
358 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI",
359 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
407 /* For NVIDIA HDA, enable snoop */
615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
625 schedule_work(&hda->irq_pending_work);
688 "hda-intel: zero azx_dev->period_bytes"))
721 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
722 struct azx *chip = &hda->chip;
727 if (!hda->irq_pending_warned) {
731 hda->irq_pending_warned = 1;
916 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
919 list_add(&hda->list, &card_list);
924 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
927 list_del_init(&hda->list);
933 struct hda_intel *hda;
945 list_for_each_entry(hda, &card_list, list) {
946 chip = &hda->chip;
947 if (!hda->probe_continued || chip->disabled ||
948 hda->runtime_pm_disabled)
961 struct hda_intel *hda;
966 hda = container_of(chip, struct hda_intel, chip);
967 if (chip->disabled || hda->init_failed || !chip->running)
974 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
980 if (hda->need_i915_power)
1001 if (!hda->need_i915_power)
1019 /* HDA controller always requires different WAKEEN for runtime suspend
1138 struct hda_intel *hda;
1144 hda = container_of(chip, struct hda_intel, chip);
1145 if (chip->disabled || hda->init_failed)
1179 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1183 wait_for_completion(&hda->probe_wait);
1184 if (hda->init_failed)
1191 if (!hda->probe_continued) {
1233 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1235 wait_for_completion(&hda->probe_wait);
1236 if (hda->init_failed)
1238 if (chip->disabled || !hda->probe_continued)
1247 * The discrete GPU cannot power down unless the HDA controller runtime
1252 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1255 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1283 hda->use_vga_switcheroo = 1;
1303 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1307 if (!hda->use_vga_switcheroo)
1316 hda->vga_switcheroo_registered = 1;
1333 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1336 if (hda->freed)
1349 hda->init_failed = 1; /* to be sure */
1350 complete_all(&hda->probe_wait);
1352 if (use_vga_switcheroo(hda)) {
1353 if (chip->disabled && hda->probe_continued)
1355 if (hda->vga_switcheroo_registered) {
1393 hda->freed = 1;
1725 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1726 azx_probe_continue(&hda->chip);
1772 struct hda_intel *hda;
1782 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1783 if (!hda)
1786 chip = &hda->chip;
1798 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1799 INIT_LIST_HEAD(&hda->list);
1801 init_completion(&hda->probe_wait);
1840 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
2025 strscpy(card->driver, "HDA-Intel");
2083 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */
2093 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */
2115 struct hda_intel *hda;
2164 hda = container_of(chip, struct hda_intel, chip);
2194 hda->need_i915_power = true;
2229 schedule_delayed_work(&hda->probe_work, 0);
2233 complete_all(&hda->probe_wait);
2260 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2290 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2301 hda->runtime_pm_disabled = 1;
2318 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2324 if (chip->disabled || hda->init_failed)
2326 if (hda->probe_retry)
2330 hda->probe_continued = 1;
2332 /* Request display power well for the HDA controller or codec. For
2333 * Haswell/Broadwell, both the display HDA controller and codec need
2370 ++hda->probe_retry < 60) {
2371 schedule_delayed_work(&hda->probe_work,
2404 if (!hda->need_i915_power)
2406 complete_all(&hda->probe_wait);
2408 hda->probe_retry = 0;
2416 struct hda_intel *hda;
2421 hda = container_of(chip, struct hda_intel, chip);
2434 cancel_delayed_work_sync(&hda->probe_work);