1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Nvidia Tegra HDMI codec support
22  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
23  * accessed using vendor-defined verbs. These registers can be used for
24  * interoperability between the HDA and HDMI drivers.
31  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
33  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
38  * +---------+-------+--------+--------+
40  * +-----------------------------------|
45  * trigger to hdmi.
64  * the format is invalidated so that the HDMI codec can be disabled.
66 static void tegra_hdmi_set_format(struct hda_codec *codec,  in tegra_hdmi_set_format()  argument
72 	struct hdmi_spec *spec = codec->spec;  in tegra_hdmi_set_format()
75 	 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.  in tegra_hdmi_set_format()
78 	 * scratch register read/write for DP MST supported Tegra HDA codec.  in tegra_hdmi_set_format()
80 	if (codec->dp_mst)  in tegra_hdmi_set_format()
84 	value = snd_hda_codec_read(codec, nid, 0,  in tegra_hdmi_set_format()
89 	snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
92 	snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
97 	snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
101 	 * Bit 30 signals that the data is valid and hence that HDMI audio can  in tegra_hdmi_set_format()
109 	if (spec->hdmi_intr_trig_ctrl) {  in tegra_hdmi_set_format()
111 		 * For Tegra HDA Codec design from TEGRA234 onwards, the  in tegra_hdmi_set_format()
112 		 * Interrupt to hdmi driver is triggered by writing  in tegra_hdmi_set_format()
113 		 * non-zero values to verb 0xF80 instead of 31st bit of  in tegra_hdmi_set_format()
116 		snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
118 		snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
123 		 * in the HDMI codec. The HDMI driver will use that as trigger  in tegra_hdmi_set_format()
128 		snd_hda_codec_write(codec, nid, 0,  in tegra_hdmi_set_format()
134 				  struct hda_codec *codec,  in tegra_hdmi_pcm_prepare()  argument
141 	err = snd_hda_hdmi_generic_pcm_prepare(hinfo, codec, stream_tag,  in tegra_hdmi_pcm_prepare()
146 	/* notify the HDMI codec of the format change */  in tegra_hdmi_pcm_prepare()
147 	tegra_hdmi_set_format(codec, hinfo->nid, format);  in tegra_hdmi_pcm_prepare()
153 				  struct hda_codec *codec,  in tegra_hdmi_pcm_cleanup()  argument
156 	/* invalidate the format in the HDMI codec */  in tegra_hdmi_pcm_cleanup()
157 	tegra_hdmi_set_format(codec, hinfo->nid, 0);  in tegra_hdmi_pcm_cleanup()
159 	return snd_hda_hdmi_generic_pcm_cleanup(hinfo, codec, substream);  in tegra_hdmi_pcm_cleanup()
162 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)  in hda_find_pcm_by_type()  argument
164 	struct hdmi_spec *spec = codec->spec;  in hda_find_pcm_by_type()
167 	for (i = 0; i < spec->num_pins; i++) {  in hda_find_pcm_by_type()
170 		if (pcm->pcm_type == type)  in hda_find_pcm_by_type()
177 static int tegra_hdmi_build_pcms(struct hda_codec *codec)  in tegra_hdmi_build_pcms()  argument
183 	err = snd_hda_hdmi_generic_build_pcms(codec);  in tegra_hdmi_build_pcms()
187 	pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);  in tegra_hdmi_build_pcms()
189 		return -ENODEV;  in tegra_hdmi_build_pcms()
192 	 * Override ->prepare() and ->cleanup() operations to notify the HDMI  in tegra_hdmi_build_pcms()
193 	 * codec about format changes.  in tegra_hdmi_build_pcms()
195 	stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];  in tegra_hdmi_build_pcms()
196 	stream->ops.prepare = tegra_hdmi_pcm_prepare;  in tegra_hdmi_build_pcms()
197 	stream->ops.cleanup = tegra_hdmi_pcm_cleanup;  in tegra_hdmi_build_pcms()
203  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
204  * - 0x10de0015
205  * - 0x10de0040
210 	if (cap->ca_index == 0x00 && channels == 2)  in nvhdmi_chmap_cea_alloc_validate_get_type()
214 	if (cap->channels != channels)  in nvhdmi_chmap_cea_alloc_validate_get_type()
215 		return -1;  in nvhdmi_chmap_cea_alloc_validate_get_type()
225 		return -EINVAL;  in nvhdmi_chmap_validate()
230 static int tegra_hdmi_init(struct hda_codec *codec)  in tegra_hdmi_init()  argument
232 	struct hdmi_spec *spec = codec->spec;  in tegra_hdmi_init()
235 	err = snd_hda_hdmi_parse_codec(codec);  in tegra_hdmi_init()
237 		snd_hda_hdmi_generic_spec_free(codec);  in tegra_hdmi_init()
241 	for (i = 0; i < spec->num_cvts; i++)  in tegra_hdmi_init()
242 		snd_hda_codec_write(codec, spec->cvt_nids[i], 0,  in tegra_hdmi_init()
246 	snd_hda_hdmi_generic_init_per_pins(codec);  in tegra_hdmi_init()
248 	codec->depop_delay = 10;  in tegra_hdmi_init()
249 	spec->chmap.ops.chmap_cea_alloc_validate_get_type =  in tegra_hdmi_init()
251 	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;  in tegra_hdmi_init()
253 	spec->chmap.ops.chmap_cea_alloc_validate_get_type =  in tegra_hdmi_init()
255 	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;  in tegra_hdmi_init()
256 	spec->nv_dp_workaround = true;  in tegra_hdmi_init()
261 static int tegrahdmi_probe(struct hda_codec *codec,  in tegrahdmi_probe()  argument
267 	err = snd_hda_hdmi_generic_alloc(codec);  in tegrahdmi_probe()
271 	if (id->driver_data == MODEL_TEGRA234) {  in tegrahdmi_probe()
272 		codec->dp_mst = true;  in tegrahdmi_probe()
273 		spec = codec->spec;  in tegrahdmi_probe()
274 		spec->dyn_pin_out = true;  in tegrahdmi_probe()
275 		spec->hdmi_intr_trig_ctrl = true;  in tegrahdmi_probe()
278 	return tegra_hdmi_init(codec);  in tegrahdmi_probe()
293 	HDA_CODEC_ID_MODEL(0x10de0020, "Tegra30 HDMI",		MODEL_TEGRA),
294 	HDA_CODEC_ID_MODEL(0x10de0022, "Tegra114 HDMI",		MODEL_TEGRA),
295 	HDA_CODEC_ID_MODEL(0x10de0028, "Tegra124 HDMI",		MODEL_TEGRA),
296 	HDA_CODEC_ID_MODEL(0x10de0029, "Tegra210 HDMI/DP",	MODEL_TEGRA),
297 	HDA_CODEC_ID_MODEL(0x10de002d, "Tegra186 HDMI/DP0",	MODEL_TEGRA),
298 	HDA_CODEC_ID_MODEL(0x10de002e, "Tegra186 HDMI/DP1",	MODEL_TEGRA),
299 	HDA_CODEC_ID_MODEL(0x10de002f, "Tegra194 HDMI/DP2",	MODEL_TEGRA),
300 	HDA_CODEC_ID_MODEL(0x10de0030, "Tegra194 HDMI/DP3",	MODEL_TEGRA),
301 	HDA_CODEC_ID_MODEL(0x10de0031, "Tegra234 HDMI/DP",	MODEL_TEGRA234),
302 	HDA_CODEC_ID_MODEL(0x10de0033, "SoC 33 HDMI/DP",	MODEL_TEGRA234),
303 	HDA_CODEC_ID_MODEL(0x10de0034, "Tegra264 HDMI/DP",	MODEL_TEGRA234),
304 	HDA_CODEC_ID_MODEL(0x10de0035, "SoC 35 HDMI/DP",	MODEL_TEGRA234),
310 MODULE_DESCRIPTION("Nvidia Tegra HDMI HD-audio codec");