1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Legacy Nvidia HDMI codec support
17 #define Nv_VERB_SET_Channel_Allocation          0xF79
18 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
19 #define Nv_VERB_SET_Audio_Protection_On         0xF98
20 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
22 #define nvhdmi_master_con_nid_7x	0x04
23 #define nvhdmi_master_pin_nid_7x	0x05
27 	0x6, 0x8, 0xa, 0xc,
32 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
34 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
40 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
42 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
43 	{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
44 	{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
45 	{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
46 	{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
50 static int nvhdmi_mcp_init(struct hda_codec *codec)  in nvhdmi_mcp_init()  argument
52 	struct hdmi_spec *spec = codec->spec;  in nvhdmi_mcp_init()
54 	if (spec->multiout.max_channels == 2)  in nvhdmi_mcp_init()
55 		snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);  in nvhdmi_mcp_init()
57 		snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);  in nvhdmi_mcp_init()
58 	return 0;  in nvhdmi_mcp_init()
61 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,  in nvhdmi_8ch_7x_set_info_frame_parameters()  argument
65 	int chan = channels ? (channels - 1) : 1;  in nvhdmi_8ch_7x_set_info_frame_parameters()
69 	case 0:  in nvhdmi_8ch_7x_set_info_frame_parameters()
71 		chanmask = 0x00;  in nvhdmi_8ch_7x_set_info_frame_parameters()
74 		chanmask = 0x08;  in nvhdmi_8ch_7x_set_info_frame_parameters()
77 		chanmask = 0x0b;  in nvhdmi_8ch_7x_set_info_frame_parameters()
80 		chanmask = 0x13;  in nvhdmi_8ch_7x_set_info_frame_parameters()
87 	snd_hda_codec_write(codec, 0x1, 0,  in nvhdmi_8ch_7x_set_info_frame_parameters()
90 	snd_hda_codec_write(codec, 0x1, 0,  in nvhdmi_8ch_7x_set_info_frame_parameters()
92 			(0x71 - chan - chanmask));  in nvhdmi_8ch_7x_set_info_frame_parameters()
96 				   struct hda_codec *codec,  in nvhdmi_8ch_7x_pcm_close()  argument
99 	struct hdmi_spec *spec = codec->spec;  in nvhdmi_8ch_7x_pcm_close()
102 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,  in nvhdmi_8ch_7x_pcm_close()
103 			0, AC_VERB_SET_CHANNEL_STREAMID, 0);  in nvhdmi_8ch_7x_pcm_close()
104 	for (i = 0; i < 4; i++) {  in nvhdmi_8ch_7x_pcm_close()
106 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,  in nvhdmi_8ch_7x_pcm_close()
107 				AC_VERB_SET_CHANNEL_STREAMID, 0);  in nvhdmi_8ch_7x_pcm_close()
109 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,  in nvhdmi_8ch_7x_pcm_close()
110 				AC_VERB_SET_STREAM_FORMAT, 0);  in nvhdmi_8ch_7x_pcm_close()
113 	/* The audio hardware sends a channel count of 0x7 (8ch) when all the  in nvhdmi_8ch_7x_pcm_close()
116 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);  in nvhdmi_8ch_7x_pcm_close()
118 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);  in nvhdmi_8ch_7x_pcm_close()
122 				     struct hda_codec *codec,  in nvhdmi_8ch_7x_pcm_prepare()  argument
130 	struct hdmi_spec *spec = codec->spec;  in nvhdmi_8ch_7x_pcm_prepare()
134 	guard(mutex)(&codec->spdif_mutex);  in nvhdmi_8ch_7x_pcm_prepare()
135 	per_cvt = get_cvt(spec, 0);  in nvhdmi_8ch_7x_pcm_prepare()
136 	spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);  in nvhdmi_8ch_7x_pcm_prepare()
138 	chs = substream->runtime->channels;  in nvhdmi_8ch_7x_pcm_prepare()
140 	dataDCC2 = 0x2;  in nvhdmi_8ch_7x_pcm_prepare()
143 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))  in nvhdmi_8ch_7x_pcm_prepare()
144 		snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
146 				0,  in nvhdmi_8ch_7x_pcm_prepare()
148 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);  in nvhdmi_8ch_7x_pcm_prepare()
151 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,  in nvhdmi_8ch_7x_pcm_prepare()
152 			AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);  in nvhdmi_8ch_7x_pcm_prepare()
155 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,  in nvhdmi_8ch_7x_pcm_prepare()
160 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {  in nvhdmi_8ch_7x_pcm_prepare()
161 		snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
163 				0,  in nvhdmi_8ch_7x_pcm_prepare()
165 				spdif->ctls & 0xff);  in nvhdmi_8ch_7x_pcm_prepare()
166 		snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
168 				0,  in nvhdmi_8ch_7x_pcm_prepare()
172 	for (i = 0; i < 4; i++) {  in nvhdmi_8ch_7x_pcm_prepare()
174 			channel_id = 0;  in nvhdmi_8ch_7x_pcm_prepare()
181 		if (codec->spdif_status_reset &&  in nvhdmi_8ch_7x_pcm_prepare()
182 		(spdif->ctls & AC_DIG1_ENABLE))  in nvhdmi_8ch_7x_pcm_prepare()
183 			snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
185 				0,  in nvhdmi_8ch_7x_pcm_prepare()
187 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);  in nvhdmi_8ch_7x_pcm_prepare()
189 		snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
191 				0,  in nvhdmi_8ch_7x_pcm_prepare()
195 		snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
197 				0,  in nvhdmi_8ch_7x_pcm_prepare()
202 		if (codec->spdif_status_reset &&  in nvhdmi_8ch_7x_pcm_prepare()
203 		(spdif->ctls & AC_DIG1_ENABLE)) {  in nvhdmi_8ch_7x_pcm_prepare()
204 			snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
206 					0,  in nvhdmi_8ch_7x_pcm_prepare()
208 					spdif->ctls & 0xff);  in nvhdmi_8ch_7x_pcm_prepare()
209 			snd_hda_codec_write(codec,  in nvhdmi_8ch_7x_pcm_prepare()
211 					0,  in nvhdmi_8ch_7x_pcm_prepare()
216 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);  in nvhdmi_8ch_7x_pcm_prepare()
218 	return 0;  in nvhdmi_8ch_7x_pcm_prepare()
236 static int nvhdmi_mcp_build_pcms(struct hda_codec *codec)  in nvhdmi_mcp_build_pcms()  argument
238 	struct hdmi_spec *spec = codec->spec;  in nvhdmi_mcp_build_pcms()
241 	err = snd_hda_hdmi_simple_build_pcms(codec);  in nvhdmi_mcp_build_pcms()
242 	if (!err && spec->multiout.max_channels == 8) {  in nvhdmi_mcp_build_pcms()
243 		struct hda_pcm *info = get_pcm_rec(spec, 0);  in nvhdmi_mcp_build_pcms()
245 		info->own_chmap = true;  in nvhdmi_mcp_build_pcms()
250 static int nvhdmi_mcp_build_controls(struct hda_codec *codec)  in nvhdmi_mcp_build_controls()  argument
252 	struct hdmi_spec *spec = codec->spec;  in nvhdmi_mcp_build_controls()
257 	err = snd_hda_hdmi_simple_build_controls(codec);  in nvhdmi_mcp_build_controls()
258 	if (err < 0)  in nvhdmi_mcp_build_controls()
261 	if (spec->multiout.max_channels != 8)  in nvhdmi_mcp_build_controls()
262 		return 0;  in nvhdmi_mcp_build_controls()
265 	info = get_pcm_rec(spec, 0);  in nvhdmi_mcp_build_controls()
266 	err = snd_pcm_add_chmap_ctls(info->pcm,  in nvhdmi_mcp_build_controls()
268 				     snd_pcm_alt_chmaps, 8, 0, &chmap);  in nvhdmi_mcp_build_controls()
269 	if (err < 0)  in nvhdmi_mcp_build_controls()
271 	switch (codec->preset->vendor_id) {  in nvhdmi_mcp_build_controls()
272 	case 0x10de0002:  in nvhdmi_mcp_build_controls()
273 	case 0x10de0003:  in nvhdmi_mcp_build_controls()
274 	case 0x10de0005:  in nvhdmi_mcp_build_controls()
275 	case 0x10de0006:  in nvhdmi_mcp_build_controls()
276 		chmap->channel_mask = (1U << 2) | (1U << 8);  in nvhdmi_mcp_build_controls()
278 	case 0x10de0007:  in nvhdmi_mcp_build_controls()
279 		chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);  in nvhdmi_mcp_build_controls()
281 	return 0;  in nvhdmi_mcp_build_controls()
295 	.mask = 0,
301 	.mask = 0,
304 static int nvhdmi_mcp_probe(struct hda_codec *codec,  in nvhdmi_mcp_probe()  argument
310 	err = snd_hda_hdmi_simple_probe(codec, nvhdmi_master_con_nid_7x,  in nvhdmi_mcp_probe()
312 	if (err < 0)  in nvhdmi_mcp_probe()
315 	/* override the PCM rates, etc, as the codec doesn't give full list */  in nvhdmi_mcp_probe()
316 	spec = codec->spec;  in nvhdmi_mcp_probe()
317 	spec->pcm_playback.rates = SUPPORTED_RATES;  in nvhdmi_mcp_probe()
318 	spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;  in nvhdmi_mcp_probe()
319 	spec->pcm_playback.formats = SUPPORTED_FORMATS;  in nvhdmi_mcp_probe()
320 	spec->nv_dp_workaround = true;  in nvhdmi_mcp_probe()
322 	if (id->driver_data == MODEL_2CH)  in nvhdmi_mcp_probe()
323 		return 0;  in nvhdmi_mcp_probe()
325 	spec->multiout.max_channels = 8;  in nvhdmi_mcp_probe()
326 	spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;  in nvhdmi_mcp_probe()
328 	switch (codec->preset->vendor_id) {  in nvhdmi_mcp_probe()
329 	case 0x10de0002:  in nvhdmi_mcp_probe()
330 	case 0x10de0003:  in nvhdmi_mcp_probe()
331 	case 0x10de0005:  in nvhdmi_mcp_probe()
332 	case 0x10de0006:  in nvhdmi_mcp_probe()
333 		spec->hw_constraints_channels = &hw_constraints_2_8_channels;  in nvhdmi_mcp_probe()
335 	case 0x10de0007:  in nvhdmi_mcp_probe()
336 		spec->hw_constraints_channels = &hw_constraints_2_6_8_channels;  in nvhdmi_mcp_probe()
345 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);  in nvhdmi_mcp_probe()
347 	return 0;  in nvhdmi_mcp_probe()
360 	HDA_CODEC_ID_MODEL(0x10de0001, "MCP73 HDMI",	MODEL_2CH),
361 	HDA_CODEC_ID_MODEL(0x10de0002, "MCP77/78 HDMI",	MODEL_8CH),
362 	HDA_CODEC_ID_MODEL(0x10de0003, "MCP77/78 HDMI",	MODEL_8CH),
363 	HDA_CODEC_ID_MODEL(0x10de0004, "GPU 04 HDMI",	MODEL_8CH),
364 	HDA_CODEC_ID_MODEL(0x10de0005, "MCP77/78 HDMI",	MODEL_8CH),
365 	HDA_CODEC_ID_MODEL(0x10de0006, "MCP77/78 HDMI",	MODEL_8CH),
366 	HDA_CODEC_ID_MODEL(0x10de0007, "MCP79/7A HDMI",	MODEL_8CH),
367 	HDA_CODEC_ID_MODEL(0x10de0067, "MCP67 HDMI",	MODEL_2CH),
368 	HDA_CODEC_ID_MODEL(0x10de8001, "MCP73 HDMI",	MODEL_2CH),
369 	HDA_CODEC_ID_MODEL(0x10de8067, "MCP67/68 HDMI",	MODEL_2CH),
375 MODULE_DESCRIPTION("Legacy Nvidia HDMI HD-audio codec");