Lines Matching +full:codec +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip
22 static int cs8409_parse_auto_config(struct hda_codec *codec)
24 struct cs8409_spec *spec = codec->spec;
28 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
29 if (err < 0)
32 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
33 if (err < 0)
37 if (spec->gen.dyn_adc_switch) {
38 unsigned int done = 0;
40 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
41 int idx = spec->gen.dyn_adc_idx[i];
45 snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
50 return 0;
55 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
62 codec->spec = spec;
63 spec->codec = codec;
64 codec->power_save_node = 1;
65 mutex_init(&spec->i2c_mux);
66 INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
67 snd_hda_gen_spec_init(&spec->gen);
72 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
74 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
75 return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
78 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
81 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
82 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
86 * cs8409_enable_i2c_clock - Disable I2C clocks
87 * @codec: the codec instance
91 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
93 struct cs8409_spec *spec = codec->spec;
95 guard(mutex)(&spec->i2c_mux);
96 if (spec->i2c_clck_enabled) {
97 cs8409_vendor_coef_set(spec->codec, 0x0,
98 cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
99 spec->i2c_clck_enabled = 0;
104 * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
110 cs8409_disable_i2c_clock(spec->codec);
114 * cs8409_enable_i2c_clock - Enable I2C clocks
115 * @codec: the codec instance
119 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
121 struct cs8409_spec *spec = codec->spec;
127 * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
129 cancel_delayed_work(&spec->i2c_clk_work);
131 if (!spec->i2c_clck_enabled) {
132 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
133 spec->i2c_clck_enabled = 1;
135 queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
139 * cs8409_i2c_wait_complete - Wait for I2C transaction
140 * @codec: the codec instance
143 * Return -ETIMEDOUT if transaction wait times out.
145 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
149 return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
150 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
154 * cs8409_set_i2c_dev_addr - Set i2c address for transaction
155 * @codec: the codec instance
158 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
160 struct cs8409_spec *spec = codec->spec;
162 if (spec->dev_addr != addr) {
163 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
164 spec->dev_addr = addr;
169 * cs8409_i2c_set_page - CS8409 I2C set page register.
170 * @scodec: the codec instance
177 struct hda_codec *codec = scodec->codec;
179 if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
180 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
181 if (cs8409_i2c_wait_complete(codec) < 0)
182 return -EIO;
183 scodec->last_page = i2c_reg >> 8;
186 return 0;
190 * cs8409_i2c_read - CS8409 I2C Read.
191 * @scodec: the codec instance
194 * Returns negative on error, otherwise returns read value in bits 0-7.
198 struct hda_codec *codec = scodec->codec;
199 struct cs8409_spec *spec = codec->spec;
203 if (scodec->suspended)
204 return -EPERM;
206 guard(mutex)(&spec->i2c_mux);
207 cs8409_enable_i2c_clock(codec);
208 cs8409_set_i2c_dev_addr(codec, scodec->addr);
213 i2c_reg_data = (addr << 8) & 0x0ffff;
214 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
215 if (cs8409_i2c_wait_complete(codec) < 0)
218 /* Register in bits 15-8 and the data in 7-0 */
219 read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
221 return read_data & 0x0ff;
224 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
225 return -EIO;
229 * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
230 * @scodec: the codec instance
238 struct hda_codec *codec = scodec->codec;
239 struct cs8409_spec *spec = codec->spec;
243 if (scodec->suspended)
244 return -EPERM;
246 guard(mutex)(&spec->i2c_mux);
247 cs8409_set_i2c_dev_addr(codec, scodec->addr);
249 for (i = 0; i < count; i++) {
250 cs8409_enable_i2c_clock(codec);
254 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
255 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
257 if (cs8409_i2c_wait_complete(codec) < 0)
260 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
263 return 0;
266 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
267 return -EIO;
271 * cs8409_i2c_write - CS8409 I2C Write.
272 * @scodec: the codec instance
276 * Returns negative on error, otherwise returns 0.
280 struct hda_codec *codec = scodec->codec;
281 struct cs8409_spec *spec = codec->spec;
284 if (scodec->suspended)
285 return -EPERM;
287 guard(mutex)(&spec->i2c_mux);
289 cs8409_enable_i2c_clock(codec);
290 cs8409_set_i2c_dev_addr(codec, scodec->addr);
295 i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
296 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
298 if (cs8409_i2c_wait_complete(codec) < 0)
301 return 0;
304 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
305 return -EIO;
309 * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
310 * @scodec: the codec instance
319 struct hda_codec *codec = scodec->codec;
320 struct cs8409_spec *spec = codec->spec;
324 if (scodec->suspended)
325 return -EPERM;
327 guard(mutex)(&spec->i2c_mux);
328 cs8409_set_i2c_dev_addr(codec, scodec->addr);
330 for (i = 0; i < count; i++) {
331 cs8409_enable_i2c_clock(codec);
335 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
336 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
338 if (cs8409_i2c_wait_complete(codec) < 0)
347 return 0;
350 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
351 return -EIO;
354 static int cs8409_init(struct hda_codec *codec)
356 int ret = snd_hda_gen_init(codec);
359 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
364 static int cs8409_build_controls(struct hda_codec *codec)
368 err = snd_hda_gen_build_controls(codec);
369 if (err < 0)
371 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
373 return 0;
377 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
379 struct cs8409_spec *spec = codec->spec;
380 unsigned int ur_gpios = 0;
383 for (i = 0; i < spec->num_scodecs; i++)
384 ur_gpios |= spec->scodecs[i]->irq_mask;
386 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
387 flag ? ur_gpios : 0);
389 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
390 flag ? AC_UNSOL_ENABLED : 0);
393 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
398 * companion codec. Most of input/output PIN(s) have only basic
402 * phantom jacks. However, a companion codec may be
407 caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
408 if (caps >= 0)
409 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
412 snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
418 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
419 struct cs8409_spec *spec = codec->spec;
421 ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio);
422 return 0;
428 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct cs8409_spec *spec = codec->spec;
432 gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) |
433 (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0);
434 if (gpio_data == spec->gpio_data)
435 return 0;
436 spec->gpio_data = gpio_data;
437 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
457 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
458 uinfo->value.integer.step = 1;
459 uinfo->count = chs == 3 ? 2 : 1;
463 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
464 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
467 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
468 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
474 return 0;
479 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
480 struct cs8409_spec *spec = codec->spec;
481 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
484 long *valp = uctrl->value.integer.value;
488 if (chs & BIT(0))
489 *valp++ = cs42l42->vol[ofs];
491 *valp = cs42l42->vol[ofs+1];
494 if (chs & BIT(0))
495 *valp = cs42l42->vol[ofs];
501 return 0;
509 if (chs & BIT(0))
510 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
512 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
514 if (chs & BIT(0))
515 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
519 if (chs & BIT(0))
521 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
525 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
528 if (chs & BIT(0))
530 cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
538 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
539 struct cs8409_spec *spec = codec->spec;
540 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
543 long *valp = uctrl->value.integer.value;
547 if (chs & BIT(0))
548 cs42l42->vol[ofs] = *valp;
551 cs42l42->vol[ofs + 1] = *valp;
553 if (spec->playback_started)
557 if (chs & BIT(0))
558 cs42l42->vol[ofs] = *valp;
559 if (spec->capture_started)
566 return 0;
570 struct hda_codec *codec,
574 struct cs8409_spec *spec = codec->spec;
582 spec->playback_started = 1;
586 spec->playback_started = 0;
592 for (i = 0; i < spec->num_scodecs; i++) {
593 cs42l42 = spec->scodecs[i];
594 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
599 struct hda_codec *codec,
603 struct cs8409_spec *spec = codec->spec;
611 spec->capture_started = 1;
615 spec->capture_started = 0;
621 for (i = 0; i < spec->num_scodecs; i++) {
622 cs42l42 = spec->scodecs[i];
623 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
627 /* Configure CS42L42 slave codec for jack autodetect */
630 cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
632 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
636 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
640 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
643 /* Enable and run CS42L42 slave codec jack auto detect */
649 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
652 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
653 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
654 cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
655 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
656 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
659 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
660 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
674 (0 << CS42L42_HSDET_SET_SHIFT) |
675 (0 << CS42L42_HSBIAS_REF_SHIFT) |
676 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
744 (0 << CS42L42_HSDET_CTRL_SHIFT) |
745 (0 << CS42L42_HSDET_SET_SHIFT) |
746 (0 << CS42L42_HSBIAS_REF_SHIFT) |
747 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
759 int status_changed = 0;
764 if (cs42l42->no_type_dect) {
766 cs42l42->hp_jack_in = 1;
767 cs42l42->mic_jack_in = 0;
775 cs42l42->hp_jack_in = 0;
776 cs42l42->mic_jack_in = 0;
783 codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status);
791 int status_changed = 0;
802 /* If status values are < 0, read error has occurred. */
803 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
804 return -EIO;
813 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
818 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
820 if (cs42l42->no_type_dect) {
824 codec_dbg(cs42l42->codec,
834 cs42l42->hp_jack_in = 1;
835 cs42l42->mic_jack_in = 1;
839 cs42l42->hp_jack_in = 1;
840 cs42l42->mic_jack_in = 0;
844 cs42l42->hp_jack_in = 0;
845 cs42l42->mic_jack_in = 0;
848 codec_dbg(cs42l42->codec, "Detection done (%d)\n", type);
851 /* Enable the HPOUT ground clamp and configure the HP pull-down */
852 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
853 /* Re-Enable Tip Sense Interrupt */
854 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
864 struct hda_codec *codec = cs42l42->codec;
865 struct cs8409_spec *spec = codec->spec;
867 { CS42L42_CODEC_STATUS, 0x00 },
868 { CS42L42_DET_INT_STATUS1, 0x00 },
869 { CS42L42_DET_INT_STATUS2, 0x00 },
870 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
875 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
876 spec->gpio_data |= cs42l42->reset_gpio;
877 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
880 cs42l42->suspended = 0;
882 /* Initialize CS42L42 companion codec */
883 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
889 if (cs42l42->full_scale_vol) {
901 snd_hda_codec_allow_unsol_events(cs42l42->codec);
908 struct hda_codec *codec = cs42l42->codec;
909 struct cs8409_spec *spec = codec->spec;
910 int reg_cdc_status = 0;
912 { CS42L42_DAC_CTL2, 0x02 },
913 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
914 { CS42L42_MIXER_CHA_VOL, 0x3F },
915 { CS42L42_MIXER_ADC_VOL, 0x3F },
916 { CS42L42_MIXER_CHB_VOL, 0x3F },
917 { CS42L42_HP_CTL, 0x0D },
918 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
919 { CS42L42_ASP_CLK_CFG, 0x00 },
920 { CS42L42_PWR_CTL1, 0xFE },
921 { CS42L42_PWR_CTL2, 0x8C },
922 { CS42L42_PWR_CTL1, 0xFF },
928 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
929 true, cs42l42, CS42L42_CODEC_STATUS) < 0)
930 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
933 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
934 cs42l42->suspended = 1;
935 cs42l42->last_page = 0;
936 cs42l42->hp_jack_in = 0;
937 cs42l42->mic_jack_in = 0;
940 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
941 spec->gpio_data &= ~cs42l42->reset_gpio;
942 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
945 static void cs8409_remove(struct hda_codec *codec)
947 struct cs8409_spec *spec = codec->spec;
950 cancel_delayed_work_sync(&spec->i2c_clk_work);
951 cs8409_disable_i2c_clock(codec);
953 snd_hda_gen_remove(codec);
962 * In the case of CS8409 we do not have unsolicited events from NID's 0x24
963 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
968 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
970 struct cs8409_spec *spec = codec->spec;
971 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
979 if (res & cs42l42->irq_mask)
983 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
984 cs42l42->hp_jack_in ? 0 : PIN_OUT);
986 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
988 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
991 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
993 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
998 static void cs8409_unsol_event(struct hda_codec *codec, unsigned int res)
1000 struct cs8409_spec *spec = codec->spec;
1002 if (spec->unsol_event)
1003 spec->unsol_event(codec, res);
1005 cs8409_cs42l42_jack_unsol_event(codec, res);
1009 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
1011 struct cs8409_spec *spec = codec->spec;
1014 spec->init_done = 0;
1016 cs8409_enable_ur(codec, 0);
1018 for (i = 0; i < spec->num_scodecs; i++)
1019 cs42l42_suspend(spec->scodecs[i]);
1022 cancel_delayed_work_sync(&spec->i2c_clk_work);
1023 cs8409_disable_i2c_clock(codec);
1025 snd_hda_shutup_pins(codec);
1027 return 0;
1033 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
1037 struct cs8409_spec *spec = codec->spec;
1038 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1040 if (spec->gpio_mask) {
1041 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1042 spec->gpio_mask);
1043 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1044 spec->gpio_dir);
1045 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1046 spec->gpio_data);
1049 for (; seq->nid; seq++)
1050 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1052 if (codec->fixup_id == CS8409_BULLSEYE) {
1053 for (; seq_bullseye->nid; seq_bullseye++)
1054 cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
1057 switch (codec->fixup_id) {
1061 cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);
1064 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */
1065 cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);
1074 cs8409_enable_ur(codec, 1);
1080 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1081 struct cs8409_spec *spec = codec->spec;
1082 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1084 unsigned int nid = ((cmd >> 20) & 0x07f);
1085 unsigned int verb = ((cmd >> 8) & 0x0fff);
1088 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
1095 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1096 return 0;
1101 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1102 return 0;
1109 return spec->exec_verb(dev, cmd, flags, res);
1112 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1114 struct cs8409_spec *spec = codec->spec;
1118 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
1120 spec->exec_verb = codec->core.exec_verb;
1121 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
1123 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
1124 spec->num_scodecs = 1;
1125 spec->scodecs[CS8409_CODEC0]->codec = codec;
1127 spec->gen.suppress_auto_mute = 1;
1128 spec->gen.no_primary_hp = 1;
1129 spec->gen.suppress_vmaster = 1;
1131 spec->speaker_pdn_gpio = 0;
1134 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
1135 spec->gpio_data = 0;
1136 spec->gpio_mask = 0x03f;
1139 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
1141 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
1142 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
1144 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1146 switch (codec->fixup_id) {
1148 spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1150 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1153 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1154 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1158 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1159 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1162 spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1164 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1168 if (spec->speaker_pdn_gpio > 0) {
1169 spec->gpio_dir |= spec->speaker_pdn_gpio;
1170 spec->gpio_data |= spec->speaker_pdn_gpio;
1176 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1177 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1179 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1180 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1181 if (codec->fixup_id != CS8409_ODIN)
1182 /* Set initial DMIC volume to -26 dB */
1183 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1184 HDA_INPUT, 0, 0xff, 0x19);
1185 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1187 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1189 if (spec->speaker_pdn_gpio > 0)
1190 snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch",
1193 cs8409_enable_ur(codec, 0);
1194 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1197 cs8409_cs42l42_hw_init(codec);
1198 spec->init_done = 1;
1199 if (spec->init_done && spec->build_ctrl_done
1200 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1201 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1204 spec->build_ctrl_done = 1;
1210 if (spec->init_done && spec->build_ctrl_done
1211 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1212 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1226 * hs mic and hp are connected. Companion codec CS42L42 will
1231 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1233 struct cs8409_spec *spec = codec->spec;
1237 cs42l42 = spec->scodecs[CS8409_CODEC0];
1238 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1240 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1242 snd_hda_jack_unsol_event(codec,
1243 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1246 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1248 snd_hda_jack_unsol_event(codec,
1249 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1253 cs42l42 = spec->scodecs[CS8409_CODEC1];
1254 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1256 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1258 snd_hda_jack_unsol_event(codec,
1259 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1267 static void dolphin_hw_init(struct hda_codec *codec)
1270 struct cs8409_spec *spec = codec->spec;
1274 if (spec->gpio_mask) {
1275 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1276 spec->gpio_mask);
1277 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1278 spec->gpio_dir);
1279 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1280 spec->gpio_data);
1283 for (; seq->nid; seq++)
1284 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1286 for (i = 0; i < spec->num_scodecs; i++) {
1287 cs42l42 = spec->scodecs[i];
1292 cs8409_enable_ur(codec, 1);
1298 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1299 struct cs8409_spec *spec = codec->spec;
1300 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1302 unsigned int nid = ((cmd >> 20) & 0x07f);
1303 unsigned int verb = ((cmd >> 8) & 0x0fff);
1314 cs42l42 = spec->scodecs[CS8409_CODEC1];
1316 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1317 return 0;
1322 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1323 return 0;
1330 return spec->exec_verb(dev, cmd, flags, res);
1333 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1335 struct cs8409_spec *spec = codec->spec;
1341 snd_hda_add_verbs(codec, dolphin_init_verbs);
1343 spec->exec_verb = codec->core.exec_verb;
1344 codec->core.exec_verb = dolphin_exec_verb;
1346 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1347 spec->scodecs[CS8409_CODEC0]->codec = codec;
1348 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1349 spec->scodecs[CS8409_CODEC1]->codec = codec;
1350 spec->num_scodecs = 2;
1351 spec->gen.suppress_vmaster = 1;
1353 spec->unsol_event = dolphin_jack_unsol_event;
1355 /* GPIO 1,5 out, 0,4 in */
1356 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1357 spec->scodecs[CS8409_CODEC1]->reset_gpio;
1358 spec->gpio_data = 0;
1359 spec->gpio_mask = 0x03f;
1362 snd_hda_sequence_write(codec, dolphin_init_verbs);
1364 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1367 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1370 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1371 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1372 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1374 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1375 spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1380 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1381 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1383 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1384 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1385 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1387 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1388 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1392 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1394 cs8409_enable_ur(codec, 0);
1395 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1398 dolphin_hw_init(codec);
1399 spec->init_done = 1;
1400 if (spec->init_done && spec->build_ctrl_done) {
1401 for (i = 0; i < spec->num_scodecs; i++) {
1402 if (!spec->scodecs[i]->hp_jack_in)
1403 cs42l42_run_jack_detect(spec->scodecs[i]);
1408 spec->build_ctrl_done = 1;
1414 if (spec->init_done && spec->build_ctrl_done) {
1415 for (i = 0; i < spec->num_scodecs; i++) {
1416 if (!spec->scodecs[i]->hp_jack_in)
1417 cs42l42_run_jack_detect(spec->scodecs[i]);
1426 static int cs8409_probe(struct hda_codec *codec, const struct hda_device_id *id)
1430 if (!cs8409_alloc_spec(codec))
1431 return -ENOMEM;
1433 snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1435 codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1436 codec->bus->pci->subsystem_vendor,
1437 codec->bus->pci->subsystem_device);
1439 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1441 err = cs8409_parse_auto_config(codec);
1442 if (err < 0) {
1443 cs8409_remove(codec);
1447 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1448 return 0;
1463 HDA_CODEC_ID(0x10138409, "CS8409"),