Lines Matching +full:codec +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HD audio codec driver for Creative CA0132 chip
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
71 #define SCP_GET 1
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
163 * X-bass.
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
188 #define EFX_DIR_IN 1
194 .reqs = {0, 1},
196 .params = 1,
204 .params = 1,
212 .params = 1,
223 { .name = "X-Bass",
245 .reqs = {0, 1, 2, 3},
263 .params = 1,
271 .params = 1,
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
313 int direct; /* 0:output; 1:input*/
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
604 * enabled. X-Bass must be disabled when using these.
609 /* Between 0x16-0x1a are the X-Bass reqs. */
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
710 #define DSP_VOL_IN 1
725 .reqs = {2, 3, 1}
763 { .name = "Low (16-31",
766 { .name = "Medium (32-149",
769 { .name = "High (150-600",
897 CONTROL_FLAG_DMA = 1,
900 /* Tracker for the SPDIF-in path is bypassed/enabled */
918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
920 /* De-emphasis filter on DAC-1 disabled/enabled */
922 /* De-emphasis filter on DAC-2 disabled/enabled */
924 /* De-emphasis filter on DAC-3 disabled/enabled */
926 /* High-pass filter on ADC_B disabled/enabled */
928 /* High-pass filter on ADC_C disabled/enabled */
945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
952 /* 0: None, 1: Mic1In*/
953 CONTROL_PARAM_VIP_SOURCE = 1,
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
965 * sense given the fact the AE-5 uses it and has the ASI flag set.
1046 DSP_DOWNLOAD_FAILED = -1,
1048 DSP_DOWNLOADING = 1,
1129 /* AE-5 Control values */
1135 struct hda_codec *codec;
1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id)
1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" },
1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" },
1373 .hda_gpio_set = 1,
1395 .mmio_gpio_count = 1,
1396 .mmio_gpio_pin = { 1 },
1397 .mmio_gpio_set = { 1 },
1404 .mmio_gpio_count = 1,
1405 .mmio_gpio_pin = { 1 },
1419 .mmio_gpio_pin = { 7, 4, 1 },
1420 .mmio_gpio_set = { 0, 1, 1 },
1427 .mmio_gpio_pin = { 7, 4, 1 },
1428 .mmio_gpio_set = { 1, 1, 0 },
1442 .mmio_gpio_set = { 1, 1, 0 },
1451 .mmio_gpio_set = { 0, 1, 1 },
1494 .mmio_gpio_count = 1,
1496 .mmio_gpio_set = { 1 },
1509 .mmio_gpio_count = 1,
1511 .mmio_gpio_set = { 1 },
1525 * CA0132 codec access
1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1534 return ((response == -1) ? -1 : 0);
1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1544 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1556 static int chipio_send(struct hda_codec *codec,
1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1572 return -EIO;
1576 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1578 static int chipio_write_address(struct hda_codec *codec,
1581 struct ca0132_spec *spec = codec->spec;
1584 if (spec->curr_chip_addx == chip_addx)
1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1591 if (res != -EIO) {
1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1603 * Write data through the vendor widget -- NOT protected by the Mutex!
1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1607 struct ca0132_spec *spec = codec->spec;
1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1613 if (res != -EIO) {
1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1621 spec->curr_chip_addx = (res != -EIO) ?
1622 (spec->curr_chip_addx + 4) : ~0U;
1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1629 static int chipio_write_data_multiple(struct hda_codec *codec,
1636 codec_dbg(codec, "chipio_write_data null ptr\n");
1637 return -EINVAL;
1640 while ((count-- != 0) && (status == 0))
1641 status = chipio_write_data(codec, *data++);
1648 * Read data through the vendor widget -- NOT protected by the Mutex!
1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1652 struct ca0132_spec *spec = codec->spec;
1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1658 if (res != -EIO) {
1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1663 if (res != -EIO) {
1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1672 spec->curr_chip_addx = (res != -EIO) ?
1673 (spec->curr_chip_addx + 4) : ~0U;
1681 static int chipio_write(struct hda_codec *codec,
1684 struct ca0132_spec *spec = codec->spec;
1687 guard(mutex)(&spec->chipio_mutex);
1690 err = chipio_write_address(codec, chip_addx);
1694 return chipio_write_data(codec, data);
1701 static int chipio_write_no_mutex(struct hda_codec *codec,
1708 err = chipio_write_address(codec, chip_addx);
1712 err = chipio_write_data(codec, data);
1724 static int chipio_write_multiple(struct hda_codec *codec,
1729 struct ca0132_spec *spec = codec->spec;
1732 guard(mutex)(&spec->chipio_mutex);
1733 status = chipio_write_address(codec, chip_addx);
1737 return chipio_write_data_multiple(codec, data, count);
1744 static int chipio_read(struct hda_codec *codec,
1747 struct ca0132_spec *spec = codec->spec;
1750 guard(mutex)(&spec->chipio_mutex);
1753 err = chipio_write_address(codec, chip_addx);
1757 return chipio_read_data(codec, data);
1763 static void chipio_set_control_flag(struct hda_codec *codec,
1770 flag_bit = (flag_state ? 1 : 0);
1772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1779 static void chipio_set_control_param(struct hda_codec *codec,
1782 struct ca0132_spec *spec = codec->spec;
1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790 guard(mutex)(&spec->chipio_mutex);
1791 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1805 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1812 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1815 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1819 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1829 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1832 chipio_set_control_param_no_mutex(codec,
1834 chipio_set_control_param_no_mutex(codec,
1836 chipio_set_control_param_no_mutex(codec,
1843 static void chipio_set_stream_channels(struct hda_codec *codec,
1846 chipio_set_control_param_no_mutex(codec,
1848 chipio_set_control_param_no_mutex(codec,
1855 static void chipio_set_stream_control(struct hda_codec *codec,
1858 chipio_set_control_param_no_mutex(codec,
1860 chipio_set_control_param_no_mutex(codec,
1867 static void chipio_get_stream_control(struct hda_codec *codec,
1870 chipio_set_control_param_no_mutex(codec,
1872 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1880 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1883 chipio_set_control_param_no_mutex(codec,
1885 chipio_set_control_param_no_mutex(codec,
1892 static void chipio_set_conn_rate(struct hda_codec *codec,
1895 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1896 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1903 * 0x80-0xFF.
1905 static void chipio_8051_write_direct(struct hda_codec *codec,
1911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1915 * Writes to the 8051's exram, which has 16-bits of address space.
1916 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1917 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1919 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1922 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1926 /* Lower 8-bits. */
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1931 /* Upper 8-bits. */
1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1937 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1939 /* 8-bits of data. */
1940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1944 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1946 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1951 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1953 /* 8-bits of data. */
1954 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958 static void chipio_8051_write_exram(struct hda_codec *codec,
1961 struct ca0132_spec *spec = codec->spec;
1963 guard(mutex)(&spec->chipio_mutex);
1965 chipio_8051_set_address(codec, addr);
1966 chipio_8051_set_data(codec, data);
1969 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1972 chipio_8051_set_address(codec, addr);
1973 chipio_8051_set_data(codec, data);
1977 static void chipio_8051_read_exram(struct hda_codec *codec,
1980 chipio_8051_set_address(codec, addr);
1981 *data = chipio_8051_get_data(codec);
1984 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1987 struct ca0132_spec *spec = codec->spec;
1989 guard(mutex)(&spec->chipio_mutex);
1991 chipio_8051_set_address(codec, addr & 0xff);
1992 chipio_8051_set_data_pll(codec, data);
1995 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
1998 chipio_8051_set_address(codec, addr & 0xff);
1999 chipio_8051_set_data_pll(codec, data);
2005 static void chipio_enable_clocks(struct hda_codec *codec)
2007 struct ca0132_spec *spec = codec->spec;
2009 guard(mutex)(&spec->chipio_mutex);
2011 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2012 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2013 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2019 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2027 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2033 return -EIO;
2039 static void dspio_write_wait(struct hda_codec *codec)
2045 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2050 msleep(1);
2057 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2059 struct ca0132_spec *spec = codec->spec;
2062 dspio_write_wait(codec);
2064 guard(mutex)(&spec->chipio_mutex);
2065 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2070 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2076 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2080 -EIO : 0;
2086 static int dspio_write_multiple(struct hda_codec *codec,
2093 return -EINVAL;
2097 status = dspio_write(codec, *buffer++);
2106 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2110 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2111 if (status == -EIO)
2114 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2115 if (status == -EIO ||
2117 return -EIO;
2119 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2125 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2135 return -1;
2139 status = dspio_read(codec, buffer++);
2148 status = dspio_read(codec, &dummy);
2218 static void dspio_clear_response_queue(struct hda_codec *codec)
2226 status = dspio_read(codec, &dummy);
2230 static int dspio_get_response_data(struct hda_codec *codec)
2232 struct ca0132_spec *spec = codec->spec;
2236 if (dspio_read(codec, &data) < 0)
2237 return -EIO;
2239 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2240 spec->scp_resp_header = data;
2241 spec->scp_resp_count = data >> 27;
2242 count = spec->wait_num_data;
2243 dspio_read_multiple(codec, spec->scp_resp_data,
2244 &spec->scp_resp_count, count);
2248 return -EIO;
2254 static int dspio_send_scp_message(struct hda_codec *codec,
2261 struct ca0132_spec *spec = codec->spec;
2278 scp_send_size = data_size + 1;
2282 return -EINVAL;
2286 return -EINVAL;
2288 spec->wait_scp_header = *((unsigned int *)send_buf);
2293 spec->wait_scp_header &= 0xffff0000;
2294 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2295 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2296 spec->wait_scp = 1;
2300 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2303 spec->wait_scp = 0;
2312 } while (spec->wait_scp && time_before(jiffies, timeout));
2314 if (!spec->wait_scp) {
2316 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2317 memcpy(&ret_msg->data, spec->scp_resp_data,
2318 spec->wait_num_data);
2319 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2322 status = -EIO;
2324 spec->wait_scp = 0;
2331 * dspio_scp - Prepare and send the SCP message to DSP
2332 * @codec: the HDA codec
2344 static int dspio_scp(struct hda_codec *codec,
2358 return -EINVAL;
2361 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2362 return -EINVAL;
2366 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2367 return -EINVAL;
2379 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2384 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2399 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2403 codec_dbg(codec, "reply too long for buf\n");
2404 return -EINVAL;
2406 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2407 return -EINVAL;
2409 codec_dbg(codec, "NULL reply\n");
2410 return -EINVAL;
2416 codec_dbg(codec, "reply ill-formed or errflag set\n");
2417 return -EIO;
2426 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2429 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2433 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2436 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2443 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2448 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2449 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2454 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2458 if ((*dma_chan + 1) == 0) {
2459 codec_dbg(codec, "no free dma channels to allocate\n");
2460 return -EBUSY;
2463 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2464 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2472 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2477 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2478 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2480 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2485 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2489 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2497 static int dsp_set_run_state(struct hda_codec *codec)
2503 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2513 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2520 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2532 static int dsp_reset(struct hda_codec *codec)
2537 codec_dbg(codec, "dsp_reset\n");
2539 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2540 retry--;
2541 } while (res == -EIO && retry);
2544 codec_dbg(codec, "dsp_reset timeout\n");
2545 return -EIO;
2559 if (UC_RANGE(chip_addx, 1)) {
2562 } else if (X_RANGE_ALL(chip_addx, 1)) {
2564 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2575 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2579 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2581 return ((dma_chnlstart_reg & (1 <<
2585 static int dsp_dma_setup_common(struct hda_codec *codec,
2597 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2600 codec_dbg(codec, "dma chan num invalid\n");
2601 return -EINVAL;
2604 if (dsp_is_dma_active(codec, dma_chan)) {
2605 codec_dbg(codec, "dma already active\n");
2606 return -EBUSY;
2612 codec_dbg(codec, "invalid chip addr\n");
2613 return -ENXIO;
2619 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2622 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2626 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2629 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2633 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2635 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2637 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2639 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2641 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2644 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2647 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2651 codec_dbg(codec, "read ACTIVE Reg fail\n");
2654 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2657 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2660 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2662 codec_dbg(codec, "write ACTIVE Reg fail\n");
2666 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2668 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2671 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2674 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2676 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2679 codec_dbg(codec, "write IRQCNT Reg fail\n");
2682 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2684 codec_dbg(codec,
2690 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2696 * Setup the DSP DMA per-transfer-specific registers
2698 static int dsp_dma_setup(struct hda_codec *codec,
2713 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2714 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2716 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2719 codec_dbg(codec, "count too big\n");
2720 return -EINVAL;
2725 codec_dbg(codec, "invalid chip addr\n");
2726 return -ENXIO;
2729 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2735 addr_field <<= 1;
2737 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2739 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2743 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2746 codec_dbg(codec, "write DMACFG Reg fail\n");
2749 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2751 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2752 (code ? 0 : 1));
2754 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2757 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2760 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2762 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2764 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2768 status = chipio_write(codec,
2771 codec_dbg(codec, "write XFRCNT Reg fail\n");
2774 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2776 codec_dbg(codec,
2781 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2789 static int dsp_dma_start(struct hda_codec *codec,
2795 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2798 status = chipio_read(codec,
2802 codec_dbg(codec, "read CHNLSTART reg fail\n");
2805 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2811 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2812 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2814 codec_dbg(codec, "write CHNLSTART reg fail\n");
2817 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2825 static int dsp_dma_stop(struct hda_codec *codec,
2831 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2834 status = chipio_read(codec,
2838 codec_dbg(codec, "read CHNLSTART reg fail\n");
2841 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2846 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2847 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2849 codec_dbg(codec, "write CHNLSTART reg fail\n");
2852 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2858 * dsp_allocate_router_ports - Allocate router ports
2860 * @codec: the HDA codec
2868 static int dsp_allocate_router_ports(struct hda_codec *codec,
2878 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2883 val |= (ports_per_channel - 1) << 4;
2884 val |= num_chans - 1;
2886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2890 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2894 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2898 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2909 static int dsp_free_router_ports(struct hda_codec *codec)
2913 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2917 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2921 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2929 static int dsp_allocate_ports(struct hda_codec *codec,
2935 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2937 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2938 codec_dbg(codec, "bad rate multiple\n");
2939 return -EINVAL;
2942 status = dsp_allocate_router_ports(codec, num_chans,
2945 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2950 static int dsp_allocate_ports_format(struct hda_codec *codec,
2956 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2957 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2960 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2961 codec_dbg(codec, "bad rate multiple\n");
2962 return -EINVAL;
2965 num_chans = get_hdafmt_chs(fmt) + 1;
2967 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2973 static int dsp_free_ports(struct hda_codec *codec)
2977 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2979 status = dsp_free_router_ports(codec);
2981 codec_dbg(codec, "free router ports fail\n");
2984 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2993 struct hda_codec *codec;
3002 DMA_STATE_RUN = 1
3005 static int dma_convert_to_hda_format(struct hda_codec *codec,
3025 struct hda_codec *codec = dma->codec;
3026 struct ca0132_spec *spec = codec->spec;
3029 if (dma->dmab->area)
3030 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3032 status = snd_hda_codec_load_dsp_prepare(codec,
3033 dma->m_converter_format,
3034 dma->buf_size,
3035 dma->dmab);
3038 spec->dsp_stream_id = status;
3057 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3063 return dma->dmab->bytes;
3068 return dma->dmab->area;
3075 memcpy(dma->dmab->area, data, count);
3084 *format = dma->m_converter_format;
3089 struct ca0132_spec *spec = dma->codec->spec;
3091 return spec->dsp_stream_id;
3106 return p->magic == g_magic_value;
3111 return g_chip_addr_magic_value == p->chip_addr;
3116 return p->count == 0;
3121 return struct_size(p, data, p->count);
3140 static int dspxfr_hci_write(struct hda_codec *codec,
3147 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3148 codec_dbg(codec, "hci_write invalid params\n");
3149 return -EINVAL;
3152 count = fls->count;
3153 data = (u32 *)(fls->data);
3155 status = chipio_write(codec, data[0], data[1]);
3157 codec_dbg(codec, "hci_write chipio failed\n");
3160 count -= 2;
3167 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3169 * @codec: the HDA codec
3171 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3180 static int dspxfr_one_seg(struct hda_codec *codec,
3209 return -EINVAL;
3216 codec_dbg(codec, "hci_write\n");
3217 return dspxfr_hci_write(codec, hci_write);
3221 codec_dbg(codec, "Invalid Params\n");
3222 return -EINVAL;
3225 data = fls->data;
3226 chip_addx = fls->chip_addr;
3227 words_to_write = fls->count;
3230 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3237 codec_dbg(codec, "Invalid chip_addx Params\n");
3238 return -EINVAL;
3247 codec_dbg(codec, "dma_engine buffer NULL\n");
3248 return -EINVAL;
3252 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3253 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3254 num_chans = get_hdafmt_chs(hda_format) + 1;
3260 codec_dbg(codec, "frmsz zero\n");
3261 return -EINVAL;
3265 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3267 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3268 codec_dbg(codec,
3275 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3276 return -EINVAL;
3285 words_to_write -= remainder_words;
3289 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3293 status = dsp_dma_stop(codec, dma_chan, ovly);
3296 status = dsp_dma_setup_common(codec, chip_addx,
3303 status = dsp_dma_setup(codec, chip_addx,
3307 status = dsp_dma_start(codec, dma_chan, ovly);
3310 if (!dsp_is_dma_active(codec, dma_chan)) {
3311 codec_dbg(codec, "dspxfr:DMA did not start\n");
3312 return -EIO;
3318 status = chipio_write_multiple(codec,
3327 status = dspxfr_hci_write(codec, hci_write);
3335 dma_active = dsp_is_dma_active(codec, dma_chan);
3343 codec_dbg(codec, "+++++ DMA complete\n");
3352 words_to_write -= run_size_words;
3356 status = chipio_write_multiple(codec, chip_addx_remainder,
3364 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3366 * @codec: the HDA codec
3368 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3376 static int dspxfr_image(struct hda_codec *codec,
3383 struct ca0132_spec *spec = codec->spec;
3393 return -EINVAL;
3397 return -ENOMEM;
3399 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3400 if (!dma_engine->dmab) {
3402 return -ENOMEM;
3405 dma_engine->codec = codec;
3406 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3407 dma_engine->m_converter_format = hda_format;
3408 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3413 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3417 codec_dbg(codec, "set converter format fail\n");
3421 status = snd_hda_codec_load_dsp_prepare(codec,
3422 dma_engine->m_converter_format,
3423 dma_engine->buf_size,
3424 dma_engine->dmab);
3427 spec->dsp_stream_id = status;
3430 status = dspio_alloc_dma_chan(codec, &dma_chan);
3432 codec_dbg(codec, "alloc dmachan fail\n");
3439 status = dsp_allocate_ports_format(codec, hda_format,
3442 codec_dbg(codec, "alloc ports fail\n");
3447 status = codec_set_converter_stream_channel(codec,
3450 codec_dbg(codec, "set stream chan fail\n");
3456 codec_dbg(codec, "FLS check fail\n");
3457 status = -EINVAL;
3460 status = dspxfr_one_seg(codec, fls_data, reloc,
3474 status = dsp_free_ports(codec);
3479 status = codec_set_converter_stream_channel(codec,
3484 dspio_free_dma_chan(codec, dma_chan);
3486 if (dma_engine->dmab->area)
3487 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3488 kfree(dma_engine->dmab);
3497 static void dspload_post_setup(struct hda_codec *codec)
3499 struct ca0132_spec *spec = codec->spec;
3500 codec_dbg(codec, "---- dspload_post_setup ------\n");
3503 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3504 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3507 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3512 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3514 * @codec: the HDA codec
3517 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3524 * linear, non-constant sized element array of structures, each of which
3529 static int dspload_image(struct hda_codec *codec,
3540 codec_dbg(codec, "---- dspload_image begin ------\n");
3557 codec_dbg(codec, "Ready to program DMA\n");
3559 status = dsp_reset(codec);
3564 codec_dbg(codec, "dsp_reset() complete\n");
3565 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3571 codec_dbg(codec, "dspxfr_image() complete\n");
3573 dspload_post_setup(codec);
3574 status = dsp_set_run_state(codec);
3577 codec_dbg(codec, "LOAD FINISHED\n");
3584 static bool dspload_is_loaded(struct hda_codec *codec)
3589 status = chipio_read(codec, 0x40004, &data);
3590 if ((status < 0) || (data != 1))
3596 #define dspload_is_loaded(codec) false
3599 static bool dspload_wait_loaded(struct hda_codec *codec)
3604 if (dspload_is_loaded(codec)) {
3605 codec_info(codec, "ca0132 DSP downloaded and running\n");
3611 codec_err(codec, "ca0132 failed to download DSP\n");
3616 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3622 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3626 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3627 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3630 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3633 struct ca0132_spec *spec = codec->spec;
3639 writew(gpio_data, spec->mem_base + 0x320);
3643 * Special pci region2 commands that are only used by the AE-5. They follow
3648 * target-id, and value.
3650 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3653 struct ca0132_spec *spec = codec->spec;
3656 writel(0x0000007e, spec->mem_base + 0x210);
3657 readl(spec->mem_base + 0x210);
3658 writel(0x0000005a, spec->mem_base + 0x210);
3659 readl(spec->mem_base + 0x210);
3660 readl(spec->mem_base + 0x210);
3662 writel(0x00800005, spec->mem_base + 0x20c);
3663 writel(group, spec->mem_base + 0x804);
3665 writel(0x00800005, spec->mem_base + 0x20c);
3670 writel(write_val, spec->mem_base + 0x204);
3676 readl(spec->mem_base + 0x860);
3677 readl(spec->mem_base + 0x854);
3678 readl(spec->mem_base + 0x840);
3680 writel(0x00800004, spec->mem_base + 0x20c);
3681 writel(0x00000000, spec->mem_base + 0x210);
3682 readl(spec->mem_base + 0x210);
3683 readl(spec->mem_base + 0x210);
3689 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3692 struct ca0132_spec *spec = codec->spec;
3695 writel(0x0000007e, spec->mem_base + 0x210);
3696 readl(spec->mem_base + 0x210);
3697 writel(0x0000005a, spec->mem_base + 0x210);
3698 readl(spec->mem_base + 0x210);
3699 readl(spec->mem_base + 0x210);
3701 writel(0x00800003, spec->mem_base + 0x20c);
3702 writel(group, spec->mem_base + 0x804);
3704 writel(0x00800005, spec->mem_base + 0x20c);
3709 writel(write_val, spec->mem_base + 0x204);
3711 readl(spec->mem_base + 0x860);
3712 readl(spec->mem_base + 0x854);
3713 readl(spec->mem_base + 0x840);
3715 writel(0x00800004, spec->mem_base + 0x20c);
3716 writel(0x00000000, spec->mem_base + 0x210);
3717 readl(spec->mem_base + 0x210);
3718 readl(spec->mem_base + 0x210);
3729 static void ca0132_gpio_init(struct hda_codec *codec)
3731 struct ca0132_spec *spec = codec->spec;
3737 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3738 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3739 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3742 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3743 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3752 static void ca0132_gpio_setup(struct hda_codec *codec)
3754 struct ca0132_spec *spec = codec->spec;
3758 snd_hda_codec_write(codec, 0x01, 0,
3760 snd_hda_codec_write(codec, 0x01, 0,
3762 snd_hda_codec_write(codec, 0x01, 0,
3764 snd_hda_codec_write(codec, 0x01, 0,
3768 snd_hda_codec_write(codec, 0x01, 0,
3770 snd_hda_codec_write(codec, 0x01, 0,
3772 snd_hda_codec_write(codec, 0x01, 0,
3785 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3786 R3DI_MIC_SELECT_BIT = 1,
3787 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3802 /* Set GPIO bit 1 to 0 for rear mic */
3804 /* Set GPIO bit 1 to 1 for front microphone*/
3805 R3DI_FRONT_MIC = 1
3811 /* Set GPIO bit 2 to 1 for speaker */
3812 R3DI_LINE_OUT = 1
3815 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3817 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3818 R3DI_DSP_DOWNLOADED = 1
3822 static void r3di_gpio_mic_set(struct hda_codec *codec,
3828 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3832 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3835 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3838 snd_hda_codec_write(codec, codec->core.afg, 0,
3842 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3848 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3852 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3853 snd_hda_codec_write(codec, codec->core.afg, 0,
3858 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3860 snd_hda_codec_write(codec, codec->core.afg, 0,
3863 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3867 snd_hda_codec_write(codec, codec->core.afg, 0,
3875 struct hda_codec *codec,
3880 struct ca0132_spec *spec = codec->spec;
3882 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3888 struct hda_codec *codec,
3891 struct ca0132_spec *spec = codec->spec;
3893 if (spec->dsp_state == DSP_DOWNLOADING)
3898 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3901 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3907 struct hda_codec *codec,
3910 struct ca0132_spec *spec = codec->spec;
3912 struct snd_pcm_runtime *runtime = substream->runtime;
3914 if (spec->dsp_state != DSP_DOWNLOADED)
3918 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3919 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3920 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3925 if (spec->cur_out_type == SPEAKER_OUT)
3928 return (latency * runtime->rate) / 1000;
3935 struct hda_codec *codec,
3938 struct ca0132_spec *spec = codec->spec;
3939 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3943 struct hda_codec *codec,
3948 struct ca0132_spec *spec = codec->spec;
3949 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3954 struct hda_codec *codec,
3957 struct ca0132_spec *spec = codec->spec;
3958 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3962 struct hda_codec *codec,
3965 struct ca0132_spec *spec = codec->spec;
3966 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3973 struct hda_codec *codec,
3978 snd_hda_codec_setup_stream(codec, hinfo->nid,
3985 struct hda_codec *codec,
3988 struct ca0132_spec *spec = codec->spec;
3990 if (spec->dsp_state == DSP_DOWNLOADING)
3993 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3998 struct hda_codec *codec,
4001 struct ca0132_spec *spec = codec->spec;
4003 struct snd_pcm_runtime *runtime = substream->runtime;
4005 if (spec->dsp_state != DSP_DOWNLOADED)
4008 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4011 return (latency * runtime->rate) / 1000;
4075 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4099 * This table counts from float 0 to 1 in increments of .01, which is
4123 * This table counts from float 10 to 1000, which is the range of the x-bass
4211 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4218 CLASS(snd_hda_power, pm)(codec);
4219 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4222 return 1;
4226 return -EINVAL;
4232 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4233 struct ca0132_spec *spec = codec->spec;
4235 long *valp = ucontrol->value.integer.value;
4236 int idx = nid - TUNING_CTL_START_NID;
4238 *valp = spec->cur_ctl_vals[idx];
4246 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4247 uinfo->count = chs == 3 ? 2 : 1;
4248 uinfo->value.integer.min = 20;
4249 uinfo->value.integer.max = 180;
4250 uinfo->value.integer.step = 1;
4258 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4259 struct ca0132_spec *spec = codec->spec;
4261 long *valp = ucontrol->value.integer.value;
4264 idx = nid - TUNING_CTL_START_NID;
4266 if (spec->cur_ctl_vals[idx] == *valp)
4269 spec->cur_ctl_vals[idx] = *valp;
4271 idx = *valp - 20;
4272 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4274 return 1;
4281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4282 uinfo->count = chs == 3 ? 2 : 1;
4283 uinfo->value.integer.min = 0;
4284 uinfo->value.integer.max = 100;
4285 uinfo->value.integer.step = 1;
4293 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4294 struct ca0132_spec *spec = codec->spec;
4296 long *valp = ucontrol->value.integer.value;
4299 idx = nid - TUNING_CTL_START_NID;
4301 if (spec->cur_ctl_vals[idx] == *valp)
4304 spec->cur_ctl_vals[idx] = *valp;
4307 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4316 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4317 uinfo->count = chs == 3 ? 2 : 1;
4318 uinfo->value.integer.min = 0;
4319 uinfo->value.integer.max = 48;
4320 uinfo->value.integer.step = 1;
4328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4329 struct ca0132_spec *spec = codec->spec;
4331 long *valp = ucontrol->value.integer.value;
4334 idx = nid - TUNING_CTL_START_NID;
4336 if (spec->cur_ctl_vals[idx] == *valp)
4339 spec->cur_ctl_vals[idx] = *valp;
4342 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4344 return 1;
4348 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4350 static int add_tuning_control(struct hda_codec *codec,
4357 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4385 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4387 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4390 static int add_tuning_ctls(struct hda_codec *codec)
4396 err = add_tuning_control(codec,
4408 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4410 struct ca0132_spec *spec = codec->spec;
4413 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4414 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4416 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4420 spec->cur_ctl_vals[i] = 24;
4427 * If jack inserted, headphone will be selected, else built-in speakers
4430 static int ca0132_select_out(struct hda_codec *codec)
4432 struct ca0132_spec *spec = codec->spec;
4439 codec_dbg(codec, "ca0132_select_out\n");
4441 CLASS(snd_hda_power_pm, pm)(codec);
4443 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4446 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4449 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4452 spec->cur_out_type = HEADPHONE_OUT;
4454 spec->cur_out_type = SPEAKER_OUT;
4456 if (spec->cur_out_type == SPEAKER_OUT) {
4457 codec_dbg(codec, "ca0132_select_out speaker\n");
4460 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4465 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4470 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4472 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4474 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4476 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4480 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4482 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4485 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4487 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4490 codec_dbg(codec, "ca0132_select_out hp\n");
4493 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4498 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4503 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4505 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4507 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4509 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4513 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4515 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4518 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4520 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4527 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4528 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4529 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4531 static void ae5_mmio_select_out(struct hda_codec *codec)
4533 struct ca0132_spec *spec = codec->spec;
4543 ca0113_mmio_command_set(codec, out_cmds->group[i],
4544 out_cmds->target[i],
4545 out_cmds->vals[spec->cur_out_type][i]);
4548 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4550 struct ca0132_spec *spec = codec->spec;
4555 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4556 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4557 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4560 /* Set front L/R full range. Zero for full-range, one for redirection. */
4561 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4562 err = dspio_set_uint_param(codec, 0x96,
4567 /* When setting full-range rear, both rear and center/lfe are set. */
4568 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4569 err = dspio_set_uint_param(codec, 0x96,
4574 err = dspio_set_uint_param(codec, 0x96,
4580 * Only the AE series cards set this value when setting full-range,
4584 err = dspio_set_uint_param(codec, 0x96,
4593 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4596 struct ca0132_spec *spec = codec->spec;
4600 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4601 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4606 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4612 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4613 err = dspio_set_uint_param(codec, 0x96,
4626 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4629 struct ca0132_spec *spec = codec->spec;
4642 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4646 struct ca0132_spec *spec = codec->spec;
4650 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4654 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4655 if (quirk_data->is_ae_series)
4656 ae5_mmio_select_out(codec);
4658 if (out_info->has_hda_gpio) {
4659 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4662 if (out_info->hda_gpio_set)
4663 gpio_data |= (1 << out_info->hda_gpio_pin);
4665 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4667 snd_hda_codec_write(codec, codec->core.afg, 0,
4671 if (out_info->mmio_gpio_count) {
4672 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4673 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4674 out_info->mmio_gpio_set[i]);
4678 if (out_info->scp_cmds_count) {
4679 for (i = 0; i < out_info->scp_cmds_count; i++) {
4680 err = dspio_set_uint_param(codec,
4681 out_info->scp_cmd_mid[i],
4682 out_info->scp_cmd_req[i],
4683 out_info->scp_cmd_val[i]);
4689 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4691 if (out_info->has_chipio_write) {
4692 chipio_write(codec, out_info->chipio_write_addr,
4693 out_info->chipio_write_data);
4696 if (quirk_data->has_headphone_gain) {
4697 if (spec->cur_out_type != HEADPHONE_OUT) {
4698 if (quirk_data->is_ae_series)
4699 ae5_headphone_gain_set(codec, 2);
4701 zxr_headphone_gain_set(codec, 0);
4703 if (quirk_data->is_ae_series)
4704 ae5_headphone_gain_set(codec,
4705 spec->ae5_headphone_gain_val);
4707 zxr_headphone_gain_set(codec,
4708 spec->zxr_gain_set);
4715 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4720 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4725 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4734 * It also adds the ability to auto-detect the front headphone port.
4736 static int ca0132_alt_select_out(struct hda_codec *codec)
4738 struct ca0132_spec *spec = codec->spec;
4744 hda_nid_t headphone_nid = spec->out_pins[1];
4746 codec_dbg(codec, "%s\n", __func__);
4748 CLASS(snd_hda_power_pm, pm)(codec);
4750 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4758 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4759 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4762 spec->cur_out_type = HEADPHONE_OUT;
4764 spec->cur_out_type = SPEAKER_OUT;
4766 spec->cur_out_type = spec->out_enum_val;
4768 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4771 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4775 err = ca0132_alt_select_out_quirk_set(codec);
4779 switch (spec->cur_out_type) {
4781 codec_dbg(codec, "%s speaker\n", __func__);
4784 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4788 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4789 /* Set front L-R to output. */
4790 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4792 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4794 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4801 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4804 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4806 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4812 codec_dbg(codec, "%s hp\n", __func__);
4813 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4817 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4818 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4819 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4822 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4823 headphone_nid = spec->out_pins[2];
4824 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4825 headphone_nid = spec->out_pins[1];
4827 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4830 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4832 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4839 * If output effects are enabled, set the X-Bass effect value again to
4844 ca0132_effects_set(codec, X_BASS,
4845 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4848 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4856 err = dspio_set_uint_param(codec, 0x96,
4861 if (spec->cur_out_type == SPEAKER_OUT)
4862 err = ca0132_alt_surround_set_bass_redirection(codec,
4863 spec->bass_redirection_val);
4865 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4870 err = dspio_set_uint_param(codec, 0x96,
4875 if (spec->cur_out_type == SPEAKER_OUT) {
4876 err = ca0132_alt_set_full_range_speaker(codec);
4891 ca0132_alt_select_out(spec->codec);
4893 ca0132_select_out(spec->codec);
4895 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4897 jack->block_report = 0;
4898 snd_hda_jack_report_sync(spec->codec);
4902 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4903 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4904 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4905 static int stop_mic1(struct hda_codec *codec);
4906 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4907 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4912 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4914 struct ca0132_spec *spec = codec->spec;
4917 if (spec->dsp_state != DSP_DOWNLOADED)
4921 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4923 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4924 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4925 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4926 if (spec->cur_mic_type == DIGITAL_MIC)
4930 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4932 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4934 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4935 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4936 if (spec->cur_mic_type == DIGITAL_MIC)
4940 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4942 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4944 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4947 return 1;
4950 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4952 struct ca0132_spec *spec = codec->spec;
4955 if (spec->dsp_state != DSP_DOWNLOADED)
4958 codec_dbg(codec, "%s\n", __func__);
4960 chipio_set_stream_control(codec, 0x03, 0);
4961 chipio_set_stream_control(codec, 0x04, 0);
4964 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4965 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4966 codec_dbg(codec, "%s: off.", __func__);
4967 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4970 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4972 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4973 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4975 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4978 if (spec->in_enum_val == REAR_LINE_IN)
4987 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4990 codec_dbg(codec, "%s: on.", __func__);
4991 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4992 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4994 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4996 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5000 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5003 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5006 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5009 chipio_set_stream_control(codec, 0x03, 1);
5010 chipio_set_stream_control(codec, 0x04, 1);
5012 return 1;
5018 * If jack inserted, ext.mic will be selected, else built-in mic
5021 static int ca0132_select_mic(struct hda_codec *codec)
5023 struct ca0132_spec *spec = codec->spec;
5027 codec_dbg(codec, "ca0132_select_mic\n");
5029 CLASS(snd_hda_power_pm, pm)(codec);
5031 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5034 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5037 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5040 spec->cur_mic_type = LINE_MIC_IN;
5042 spec->cur_mic_type = DIGITAL_MIC;
5044 if (spec->cur_mic_type == DIGITAL_MIC) {
5046 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5047 ca0132_set_dmic(codec, 1);
5048 ca0132_mic_boost_set(codec, 0);
5050 ca0132_effects_set(codec, VOICE_FOCUS,
5051 spec->effects_switch
5052 [VOICE_FOCUS - EFFECT_START_NID]);
5055 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5056 ca0132_set_dmic(codec, 0);
5057 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5059 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5068 * The front mic has no jack-detection, so the only way to switch to it
5071 static int ca0132_alt_select_in(struct hda_codec *codec)
5073 struct ca0132_spec *spec = codec->spec;
5076 codec_dbg(codec, "%s\n", __func__);
5078 CLASS(snd_hda_power_pm, pm)(codec);
5080 chipio_set_stream_control(codec, 0x03, 0);
5081 chipio_set_stream_control(codec, 0x04, 0);
5083 spec->cur_mic_type = spec->in_enum_val;
5085 switch (spec->cur_mic_type) {
5090 ca0113_mmio_gpio_set(codec, 0, false);
5097 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5101 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5105 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5107 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5109 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5111 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5118 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5119 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5121 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5123 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5125 chipio_set_stream_control(codec, 0x03, 1);
5126 chipio_set_stream_control(codec, 0x04, 1);
5129 chipio_write(codec, 0x18B098, 0x0000000C);
5130 chipio_write(codec, 0x18B09C, 0x0000000C);
5133 chipio_write(codec, 0x18B098, 0x0000000C);
5134 chipio_write(codec, 0x18B09C, 0x000000CC);
5137 chipio_write(codec, 0x18B098, 0x0000000C);
5138 chipio_write(codec, 0x18B09C, 0x0000004C);
5143 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5146 ca0132_mic_boost_set(codec, 0);
5150 ca0113_mmio_gpio_set(codec, 0, false);
5153 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5156 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5159 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5160 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5162 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5164 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5170 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5171 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5173 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5179 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5184 chipio_write(codec, 0x18B098, 0x00000000);
5185 chipio_write(codec, 0x18B09C, 0x00000000);
5190 chipio_set_stream_control(codec, 0x03, 1);
5191 chipio_set_stream_control(codec, 0x04, 1);
5197 ca0113_mmio_gpio_set(codec, 0, true);
5198 ca0113_mmio_gpio_set(codec, 5, false);
5202 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5206 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5214 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5215 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5217 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5219 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5221 chipio_set_stream_control(codec, 0x03, 1);
5222 chipio_set_stream_control(codec, 0x04, 1);
5226 chipio_write(codec, 0x18B098, 0x0000000C);
5227 chipio_write(codec, 0x18B09C, 0x000000CC);
5230 chipio_write(codec, 0x18B098, 0x0000000C);
5231 chipio_write(codec, 0x18B09C, 0x0000004C);
5236 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5239 ca0132_cvoice_switch_set(codec);
5247 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5251 struct ca0132_spec *spec = codec->spec;
5256 nid = spec->shared_out_nid;
5259 nid = spec->shared_mic_nid;
5273 * They return 0 if no changed. Return 1 if changed.
5275 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5277 struct ca0132_spec *spec = codec->spec;
5282 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5288 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5291 return 1;
5297 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5299 struct ca0132_spec *spec = codec->spec;
5303 int idx = nid - EFFECT_START_NID;
5311 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5313 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5314 channel_cfg = spec->channel_cfg_val;
5324 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5327 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5328 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5333 && (spec->cur_mic_type != REAR_LINE_IN)) {
5334 if (spec->effects_switch[CRYSTAL_VOICE -
5337 if (spec->effects_switch[VOICE_FOCUS -
5340 val = 1;
5344 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5352 && (spec->cur_mic_type != REAR_LINE_IN)) {
5353 if (spec->effects_switch[CRYSTAL_VOICE -
5355 if (spec->effects_switch[NOISE_REDUCTION -
5363 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5368 spec->in_enum_val == REAR_LINE_IN)
5372 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5376 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5382 return 1;
5388 static int ca0132_pe_switch_set(struct hda_codec *codec)
5390 struct ca0132_spec *spec = codec->spec;
5394 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5395 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5398 ca0132_alt_select_out(codec);
5400 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5404 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5410 static int stop_mic1(struct hda_codec *codec)
5412 struct ca0132_spec *spec = codec->spec;
5413 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5416 snd_hda_codec_write(codec, spec->adcs[0], 0,
5423 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5425 struct ca0132_spec *spec = codec->spec;
5428 snd_hda_codec_write(codec, spec->adcs[0], 0,
5436 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5438 struct ca0132_spec *spec = codec->spec;
5443 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5444 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5446 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5450 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5453 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5456 oldval = stop_mic1(codec);
5458 ret |= ca0132_alt_set_vipsource(codec, 1);
5460 ret |= ca0132_set_vipsource(codec, 1);
5461 resume_mic1(codec, oldval);
5465 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5467 struct ca0132_spec *spec = codec->spec;
5471 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5474 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5480 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5482 struct ca0132_spec *spec = codec->spec;
5485 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5490 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5495 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5501 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5504 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5506 ca0113_mmio_gpio_set(codec, 1, val);
5514 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5519 struct ca0132_spec *spec = codec->spec;
5524 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5527 ca0132_alt_select_out(codec);
5529 ca0132_select_out(codec);
5531 return 1;
5536 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5538 ca0132_select_mic(codec);
5539 return 1;
5544 ca0132_alt_select_out(codec);
5546 ca0132_select_out(codec);
5547 return 1;
5551 ca0132_select_mic(codec);
5552 return 1;
5556 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5562 guard(mutex)(&codec->control_mutex);
5563 pval = kcontrol->private_value;
5564 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5567 kcontrol->private_value = pval;
5574 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5577 CLASS(snd_hda_power, pm)(codec);
5579 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5592 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5604 y = 1;
5606 CLASS(snd_hda_power, pm)(codec);
5612 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5613 ca0132_effects[i].reqs[1],
5614 &(lookup[idx - 1]), sizeof(unsigned int));
5621 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5632 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5633 struct ca0132_spec *spec = codec->spec;
5634 long *valp = ucontrol->value.integer.value;
5638 *valp = spec->bass_redirect_xover_freq;
5640 *valp = spec->xbass_xover_freq;
5648 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5649 struct ca0132_spec *spec = codec->spec;
5651 long *valp = ucontrol->value.integer.value;
5652 int idx = nid - OUT_EFFECT_START_NID;
5654 *valp = spec->fx_ctl_val[idx];
5659 * The X-bass crossover starts at 10hz, so the min is 1. The
5665 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5666 uinfo->count = 1;
5667 uinfo->value.integer.min = 1;
5668 uinfo->value.integer.max = 100;
5669 uinfo->value.integer.step = 1;
5679 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5680 uinfo->count = chs == 3 ? 2 : 1;
5681 uinfo->value.integer.min = 0;
5682 uinfo->value.integer.max = 100;
5683 uinfo->value.integer.step = 1;
5691 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5692 struct ca0132_spec *spec = codec->spec;
5694 long *valp = ucontrol->value.integer.value;
5699 cur_val = &spec->bass_redirect_xover_freq;
5701 cur_val = &spec->xbass_xover_freq;
5711 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5713 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5721 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5722 struct ca0132_spec *spec = codec->spec;
5724 long *valp = ucontrol->value.integer.value;
5727 idx = nid - EFFECT_START_NID;
5729 if (spec->fx_ctl_val[idx] == *valp)
5732 spec->fx_ctl_val[idx] = *valp;
5735 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5744 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5755 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5756 uinfo->count = 1;
5757 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5758 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5759 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5760 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5761 strscpy(uinfo->value.enumerated.name, namestr);
5768 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5769 struct ca0132_spec *spec = codec->spec;
5771 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5778 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5779 struct ca0132_spec *spec = codec->spec;
5780 int sel = ucontrol->value.enumerated.item[0];
5786 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5789 spec->mic_boost_enum_val = sel;
5791 if (spec->in_enum_val != REAR_LINE_IN)
5792 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5794 return 1;
5798 * Sound BlasterX AE-5 Headphone Gain Controls.
5807 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5808 uinfo->count = 1;
5809 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5810 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5811 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5813 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5815 strscpy(uinfo->value.enumerated.name, namestr);
5822 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5823 struct ca0132_spec *spec = codec->spec;
5825 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5832 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5833 struct ca0132_spec *spec = codec->spec;
5834 int sel = ucontrol->value.enumerated.item[0];
5840 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5843 spec->ae5_headphone_gain_val = sel;
5845 if (spec->out_enum_val == HEADPHONE_OUT)
5846 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5848 return 1;
5852 * Sound BlasterX AE-5 sound filter enumerated control.
5861 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5862 uinfo->count = 1;
5863 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5864 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5865 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5867 ae5_filter_presets[uinfo->value.enumerated.item].name);
5868 strscpy(uinfo->value.enumerated.name, namestr);
5875 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5876 struct ca0132_spec *spec = codec->spec;
5878 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5885 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5886 struct ca0132_spec *spec = codec->spec;
5887 int sel = ucontrol->value.enumerated.item[0];
5893 codec_dbg(codec, "ae5_sound_filter: %s\n",
5896 spec->ae5_filter_val = sel;
5898 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5901 return 1;
5906 * front microphone has no auto-detect, and we need a way to set the rear
5907 * as line-in
5912 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5913 uinfo->count = 1;
5914 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5915 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5916 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5917 strscpy(uinfo->value.enumerated.name,
5918 in_src_str[uinfo->value.enumerated.item]);
5925 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5926 struct ca0132_spec *spec = codec->spec;
5928 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5935 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5936 struct ca0132_spec *spec = codec->spec;
5937 int sel = ucontrol->value.enumerated.item[0];
5941 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5942 * line-in.
5950 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5953 spec->in_enum_val = sel;
5955 ca0132_alt_select_in(codec);
5957 return 1;
5964 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5965 uinfo->count = 1;
5966 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5967 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5968 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5969 strscpy(uinfo->value.enumerated.name,
5970 out_type_str[uinfo->value.enumerated.item]);
5977 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5978 struct ca0132_spec *spec = codec->spec;
5980 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5987 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5988 struct ca0132_spec *spec = codec->spec;
5989 int sel = ucontrol->value.enumerated.item[0];
5996 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5999 spec->out_enum_val = sel;
6001 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6004 ca0132_alt_select_out(codec);
6006 return 1;
6015 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6016 uinfo->count = 1;
6017 uinfo->value.enumerated.items = items;
6018 if (uinfo->value.enumerated.item >= items)
6019 uinfo->value.enumerated.item = items - 1;
6020 strscpy(uinfo->value.enumerated.name,
6021 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6028 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6029 struct ca0132_spec *spec = codec->spec;
6031 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6038 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6039 struct ca0132_spec *spec = codec->spec;
6040 int sel = ucontrol->value.enumerated.item[0];
6046 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6049 spec->channel_cfg_val = sel;
6051 if (spec->out_enum_val == SPEAKER_OUT)
6052 ca0132_alt_select_out(codec);
6054 return 1;
6068 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6069 uinfo->count = 1;
6070 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6071 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6072 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6073 strscpy(uinfo->value.enumerated.name,
6074 out_svm_set_enum_str[uinfo->value.enumerated.item]);
6081 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6082 struct ca0132_spec *spec = codec->spec;
6084 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6091 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6092 struct ca0132_spec *spec = codec->spec;
6093 int sel = ucontrol->value.enumerated.item[0];
6095 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6101 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6104 spec->smart_volume_setting = sel;
6110 case 1:
6121 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6123 return 1;
6132 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6133 uinfo->count = 1;
6134 uinfo->value.enumerated.items = items;
6135 if (uinfo->value.enumerated.item >= items)
6136 uinfo->value.enumerated.item = items - 1;
6137 strscpy(uinfo->value.enumerated.name,
6138 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6145 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6146 struct ca0132_spec *spec = codec->spec;
6148 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6155 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6156 struct ca0132_spec *spec = codec->spec;
6158 int sel = ucontrol->value.enumerated.item[0];
6164 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6171 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6179 spec->eq_preset_val = sel;
6181 return 1;
6189 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6190 uinfo->count = 1;
6191 uinfo->value.enumerated.items = items;
6192 if (uinfo->value.enumerated.item >= items)
6193 uinfo->value.enumerated.item = items - 1;
6194 strscpy(uinfo->value.enumerated.name,
6195 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6202 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6203 struct ca0132_spec *spec = codec->spec;
6205 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6212 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6213 struct ca0132_spec *spec = codec->spec;
6215 int sel = ucontrol->value.enumerated.item[0];
6220 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6228 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6236 spec->voicefx_val = sel;
6238 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6241 return 1;
6247 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6248 struct ca0132_spec *spec = codec->spec;
6251 long *valp = ucontrol->value.integer.value;
6255 if (ch & 1) {
6256 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6260 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6268 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6273 if (nid == spec->input_pins[0]) {
6274 *valp = spec->cur_mic_boost;
6279 *valp = spec->zxr_gain_set;
6284 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6289 *valp = spec->bass_redirection_val;
6299 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6300 struct ca0132_spec *spec = codec->spec;
6303 long *valp = ucontrol->value.integer.value;
6305 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6308 CLASS(snd_hda_power, pm)(codec);
6311 if (ch & 1) {
6312 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6316 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6324 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6325 return ca0132_pe_switch_set(codec);
6330 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6331 return ca0132_cvoice_switch_set(codec);
6337 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6338 return ca0132_effects_set(codec, nid, *valp);
6342 if (nid == spec->input_pins[0]) {
6343 spec->cur_mic_boost = *valp;
6345 if (spec->in_enum_val != REAR_LINE_IN)
6346 return ca0132_mic_boost_set(codec, *valp);
6349 if (spec->cur_mic_type != DIGITAL_MIC)
6350 return ca0132_mic_boost_set(codec, *valp);
6353 return 1;
6357 spec->zxr_gain_set = *valp;
6358 if (spec->cur_out_type == HEADPHONE_OUT)
6359 return zxr_headphone_gain_set(codec, *valp);
6365 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6366 if (spec->cur_out_type == SPEAKER_OUT)
6367 ca0132_alt_set_full_range_speaker(codec);
6373 spec->bass_redirection_val = *valp;
6374 if (spec->cur_out_type == SPEAKER_OUT)
6375 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6380 return 1;
6391 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6393 struct ca0132_spec *spec = codec->spec;
6402 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6404 dspio_set_uint_param(codec,
6409 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6411 dspio_set_uint_param(codec,
6413 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6416 dspio_set_uint_param(codec,
6424 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6425 struct ca0132_spec *spec = codec->spec;
6435 nid = spec->shared_out_nid;
6436 scoped_guard(mutex, &codec->control_mutex) {
6437 pval = kcontrol->private_value;
6438 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6440 kcontrol->private_value = pval;
6445 nid = spec->shared_mic_nid;
6446 scoped_guard(mutex, &codec->control_mutex) {
6447 pval = kcontrol->private_value;
6448 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6450 kcontrol->private_value = pval;
6462 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6463 struct ca0132_spec *spec = codec->spec;
6466 long *valp = ucontrol->value.integer.value;
6469 if (ch & 1) {
6470 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6474 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6483 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6484 struct ca0132_spec *spec = codec->spec;
6487 long *valp = ucontrol->value.integer.value;
6490 int changed = 1;
6493 if (ch & 1) {
6494 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6498 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6503 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6508 CLASS(snd_hda_power, pm)(codec);
6509 guard(mutex)(&codec->control_mutex);
6510 pval = kcontrol->private_value;
6511 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6514 kcontrol->private_value = pval;
6528 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6529 struct ca0132_spec *spec = codec->spec;
6532 long *valp = ucontrol->value.integer.value;
6545 if (ch & 1) {
6546 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6550 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6554 CLASS(snd_hda_power, pm)(codec);
6555 ca0132_alt_dsp_volume_put(codec, vnid);
6556 guard(mutex)(&codec->control_mutex);
6563 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6564 struct ca0132_spec *spec = codec->spec;
6574 nid = spec->shared_out_nid;
6575 scoped_guard(mutex, &codec->control_mutex) {
6576 pval = kcontrol->private_value;
6577 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6579 kcontrol->private_value = pval;
6584 nid = spec->shared_mic_nid;
6585 scoped_guard(mutex, &codec->control_mutex) {
6586 pval = kcontrol->private_value;
6587 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6589 kcontrol->private_value = pval;
6599 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6605 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6622 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6626 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6634 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6637 struct ca0132_spec *spec = codec->spec;
6641 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6650 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6653 static int add_voicefx(struct hda_codec *codec)
6657 VOICEFX, 1, 0, HDA_INPUT);
6661 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6665 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6669 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6673 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6674 snd_ctl_new1(&knew, codec));
6682 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6686 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6690 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6691 snd_ctl_new1(&knew, codec));
6699 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6703 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6707 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6708 snd_ctl_new1(&knew, codec));
6716 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6720 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6724 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6725 snd_ctl_new1(&knew, codec));
6733 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6736 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6737 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6739 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6740 snd_ctl_new1(&knew, codec));
6743 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6746 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6747 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6749 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6750 snd_ctl_new1(&knew, codec));
6755 * channel on speakers that are set as not being full-range. On configurations
6757 * replacement for X-Bass on configurations with an LFE channel.
6759 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6763 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6771 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6772 snd_ctl_new1(&knew, codec));
6775 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6779 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6782 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6783 snd_ctl_new1(&knew, codec));
6788 * because the front microphone has no auto-detect, and Line-in has to be set
6791 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6795 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6799 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6800 snd_ctl_new1(&knew, codec));
6807 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6811 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6815 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6816 snd_ctl_new1(&knew, codec));
6821 * Add headphone gain enumerated control for the AE-5. This switches between
6822 * three modes, low, medium, and high. When non-headphone outputs are selected,
6825 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6828 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6829 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6833 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6834 snd_ctl_new1(&knew, codec));
6838 * Add sound filter enumerated control for the AE-5. This adds three different
6842 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6845 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6846 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6850 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6851 snd_ctl_new1(&knew, codec));
6854 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6858 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6860 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6861 snd_ctl_new1(&knew, codec));
6891 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6896 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6898 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6903 if (hinfo->channels_max == 6) {
6904 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6906 elem, hinfo->channels_max, 0, &chmap);
6908 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6922 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6923 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6926 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6927 0x12, 1, HDA_INPUT),
6929 VNID_HP_SEL, 1, HDA_OUTPUT),
6931 VNID_AMIC1_SEL, 1, HDA_INPUT),
6933 VNID_HP_ASEL, 1, HDA_OUTPUT),
6935 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6940 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6949 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6950 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6958 VNID_HP_ASEL, 1, HDA_OUTPUT),
6971 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6972 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6980 VNID_HP_ASEL, 1, HDA_OUTPUT),
6984 static int ca0132_build_controls(struct hda_codec *codec)
6986 struct ca0132_spec *spec = codec->spec;
6991 for (i = 0; i < spec->num_mixers; i++) {
6992 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6998 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6999 spec->tlv);
7000 snd_hda_add_vmaster(codec, "Master Playback Volume",
7001 spec->tlv, ca0132_alt_follower_pfxs,
7003 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7006 true, 0, &spec->vmaster_mute.sw_kctl);
7018 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7023 err = add_fx_switch(codec, ca0132_effects[i].nid,
7030 * If codec has use_alt_controls set to true, add effect level sliders,
7035 err = ca0132_alt_add_svm_enum(codec);
7039 err = add_ca0132_alt_eq_presets(codec);
7043 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7048 err = add_fx_switch(codec, CRYSTAL_VOICE,
7049 "Enable InFX", 1);
7053 num_sliders = OUT_EFFECTS_COUNT - 1;
7055 err = ca0132_alt_add_effect_slider(codec,
7063 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7064 "X-Bass Crossover", EFX_DIR_OUT);
7069 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7074 err = add_fx_switch(codec, CRYSTAL_VOICE,
7075 "CrystalVoice", 1);
7079 err = add_voicefx(codec);
7084 * If the codec uses alt_functions, you need the enumerated controls
7089 err = ca0132_alt_add_output_enum(codec);
7092 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7095 err = ca0132_alt_add_front_full_range_switch(codec);
7098 err = ca0132_alt_add_rear_full_range_switch(codec);
7101 err = ca0132_alt_add_bass_redirection_crossover(codec);
7104 err = ca0132_alt_add_bass_redirection_switch(codec);
7107 err = ca0132_alt_add_mic_boost_enum(codec);
7112 * header on the card, and aux-in is handled by the DBPro board.
7115 err = ca0132_alt_add_input_enum(codec);
7124 err = ae5_add_headphone_gain_enum(codec);
7127 err = ae5_add_sound_filter_enum(codec);
7132 err = zxr_add_headphone_gain_switch(codec);
7141 add_tuning_ctls(codec);
7144 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7148 if (spec->dig_out) {
7149 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7150 spec->dig_out);
7153 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7156 /* spec->multiout.share_spdif = 1; */
7159 if (spec->dig_in) {
7160 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7166 ca0132_alt_add_chmap_ctls(codec);
7171 static int dbpro_build_controls(struct hda_codec *codec)
7173 struct ca0132_spec *spec = codec->spec;
7176 if (spec->dig_out) {
7177 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7178 spec->dig_out);
7183 if (spec->dig_in) {
7184 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7196 .substreams = 1,
7207 .substreams = 1,
7218 .substreams = 1,
7230 .substreams = 1,
7235 static int ca0132_build_pcms(struct hda_codec *codec)
7237 struct ca0132_spec *spec = codec->spec;
7240 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7242 return -ENOMEM;
7244 info->own_chmap = true;
7245 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7248 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7249 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7250 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7251 spec->multiout.max_channels;
7252 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7253 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7254 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7258 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7260 return -ENOMEM;
7261 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7263 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7264 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7267 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7269 return -ENOMEM;
7270 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7271 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7272 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7274 if (!spec->dig_out && !spec->dig_in)
7277 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7279 return -ENOMEM;
7280 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7281 if (spec->dig_out) {
7282 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7284 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7286 if (spec->dig_in) {
7287 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7289 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7295 static int dbpro_build_pcms(struct hda_codec *codec)
7297 struct ca0132_spec *spec = codec->spec;
7300 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7302 return -ENOMEM;
7303 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7304 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7308 if (!spec->dig_out && !spec->dig_in)
7311 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7313 return -ENOMEM;
7314 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7315 if (spec->dig_out) {
7316 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7318 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7320 if (spec->dig_in) {
7321 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7323 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7329 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7332 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7333 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7334 snd_hda_codec_write(codec, pin, 0,
7338 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7339 snd_hda_codec_write(codec, dac, 0,
7343 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7346 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7347 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7348 snd_hda_codec_write(codec, pin, 0,
7352 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7353 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7357 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7359 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7364 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7368 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7370 snd_hda_override_amp_caps(codec, nid, dir, caps);
7374 * Switch between Digital built-in mic and analog mic.
7376 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7378 struct ca0132_spec *spec = codec->spec;
7383 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7385 oldval = stop_mic1(codec);
7386 ca0132_set_vipsource(codec, 0);
7388 /* set DMic input as 2-ch */
7390 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7392 val = spec->dmic_ctl;
7394 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7397 if (!(spec->dmic_ctl & 0x20))
7398 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7402 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7404 val = spec->dmic_ctl;
7407 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7410 if (!(spec->dmic_ctl & 0x20))
7411 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7413 ca0132_set_vipsource(codec, 1);
7414 resume_mic1(codec, oldval);
7420 static void ca0132_init_dmic(struct hda_codec *codec)
7422 struct ca0132_spec *spec = codec->spec;
7430 * Bit 2-0: MPIO select
7432 * Bit 7-4: reserved
7435 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7439 * Bit 2-0: Data1 MPIO select
7441 * Bit 6-4: Data2 MPIO select
7445 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7448 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7449 * Bit 3-0: Channel mask
7460 spec->dmic_ctl = val;
7461 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7468 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7470 struct ca0132_spec *spec = codec->spec;
7472 guard(mutex)(&spec->chipio_mutex);
7474 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7475 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7478 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7480 struct ca0132_spec *spec = codec->spec;
7483 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7484 snd_hda_codec_update_widgets(codec);
7486 for (i = 0; i < spec->multiout.num_dacs; i++)
7487 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7489 for (i = 0; i < spec->num_outputs; i++)
7490 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7492 for (i = 0; i < spec->num_inputs; i++) {
7493 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7494 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7500 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7506 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7515 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7525 if (dsp_is_dma_active(codec, i)) {
7526 status = dspio_free_dma_chan(codec, i);
7528 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7535 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7539 * cause of most of the no-audio on startup issues were due to improperly
7553 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7555 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7558 struct ca0132_spec *spec = codec->spec;
7565 scoped_guard(mutex, &spec->chipio_mutex) {
7567 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7570 chipio_set_stream_control(codec,
7581 ca0132_alt_free_active_dma_channels(codec);
7583 guard(mutex)(&spec->chipio_mutex);
7586 chipio_set_stream_channels(codec, 0x0c, 6);
7589 chipio_set_stream_control(codec,
7590 dsp_dma_stream_ids[i], 1);
7598 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7600 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7601 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7606 * is 1.
7608 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7621 * 0x00-0x1f: HDA audio stream input/output ports.
7622 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7623 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7624 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7625 * 0xe0-0xff: DAC/ADC audio input/output ports.
7641 static void chipio_remap_stream(struct hda_codec *codec,
7647 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7659 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7668 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7669 __func__, remap_data->stream_id);
7673 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7677 for (i = 0; i < remap_data->count; i++) {
7678 chipio_write_no_mutex(codec,
7679 stream_offset + remap_data->offset[i],
7680 remap_data->value[i]);
7684 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7691 /* Non-zero values are floating point 0.000198. */
7696 /* Non-zero values are floating point 0.000220. */
7701 /* Non-zero values are floating point 0.000100. */
7708 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7710 struct ca0132_spec *spec = codec->spec;
7731 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7735 for (i = start_req; i < end_req + 1; i++)
7736 dspio_set_uint_param(codec, 0x96, i, tmp);
7740 for (i = start_req; i < end_req + 1; i++)
7741 dspio_set_uint_param(codec, 0x96, i, tmp);
7745 dspio_set_uint_param(codec, 0x96,
7750 * Initialize mic for non-chromebook ca0132 implementations.
7752 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7754 struct ca0132_spec *spec = codec->spec;
7757 /* Mic 1 Setup */
7758 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7759 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7761 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7765 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7768 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7769 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7771 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7773 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7782 static void sbz_connect_streams(struct hda_codec *codec)
7784 struct ca0132_spec *spec = codec->spec;
7786 guard(mutex)(&spec->chipio_mutex);
7788 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7791 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7794 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7795 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7796 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7797 chipio_set_stream_channels(codec, 0x14, 2);
7798 chipio_set_stream_control(codec, 0x14, 1);
7800 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7809 static void sbz_chipio_startup_data(struct hda_codec *codec)
7812 struct ca0132_spec *spec = codec->spec;
7814 guard(mutex)(&spec->chipio_mutex);
7815 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7818 chipio_remap_stream(codec, &stream_remap_data[0]);
7823 dsp_out_remap_data = &stream_remap_data[1];
7836 chipio_remap_stream(codec, dsp_out_remap_data);
7838 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7841 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7843 struct ca0132_spec *spec = codec->spec;
7846 chipio_set_stream_control(codec, 0x03, 0);
7847 chipio_set_stream_control(codec, 0x04, 0);
7849 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7850 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7853 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7855 chipio_set_stream_control(codec, 0x03, 1);
7856 chipio_set_stream_control(codec, 0x04, 1);
7860 chipio_write(codec, 0x18b098, 0x0000000c);
7861 chipio_write(codec, 0x18b09C, 0x0000000c);
7864 chipio_write(codec, 0x18b098, 0x0000000c);
7865 chipio_write(codec, 0x18b09c, 0x0000004c);
7872 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7874 struct ca0132_spec *spec = codec->spec;
7876 chipio_8051_write_direct(codec, 0x93, 0x10);
7877 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7879 writeb(0xff, spec->mem_base + 0x304);
7880 writeb(0xff, spec->mem_base + 0x304);
7881 writeb(0xff, spec->mem_base + 0x304);
7882 writeb(0xff, spec->mem_base + 0x304);
7883 writeb(0x00, spec->mem_base + 0x100);
7884 writeb(0xff, spec->mem_base + 0x304);
7885 writeb(0x00, spec->mem_base + 0x100);
7886 writeb(0xff, spec->mem_base + 0x304);
7887 writeb(0x00, spec->mem_base + 0x100);
7888 writeb(0xff, spec->mem_base + 0x304);
7889 writeb(0x00, spec->mem_base + 0x100);
7890 writeb(0xff, spec->mem_base + 0x304);
7892 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7893 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7894 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7897 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7902 * AE-5's registry values in Windows.
7904 chipio_set_control_param(codec, 3, 0);
7907 * change colors on the external LED strip connected to the AE-5.
7909 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7912 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7914 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7917 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7919 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7920 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7921 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7922 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7923 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7926 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7928 struct ca0132_spec *spec = codec->spec;
7930 guard(mutex)(&spec->chipio_mutex);
7932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7934 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7936 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7938 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7939 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7940 chipio_set_stream_channels(codec, 0x18, 6);
7941 chipio_set_stream_control(codec, 0x18, 1);
7943 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7945 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7947 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7950 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7952 struct ca0132_spec *spec = codec->spec;
7954 guard(mutex)(&spec->chipio_mutex);
7956 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7957 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7958 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7959 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7961 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7962 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7963 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7964 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7965 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7966 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7967 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7968 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7969 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7970 ca0113_mmio_gpio_set(codec, 0, true);
7971 ca0113_mmio_gpio_set(codec, 1, true);
7972 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7974 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7976 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7977 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7980 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7982 struct ca0132_spec *spec = codec->spec;
7984 guard(mutex)(&spec->chipio_mutex);
7987 chipio_remap_stream(codec, &stream_remap_data[1]);
7989 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7990 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7991 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7992 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7993 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7994 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7995 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7996 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7999 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8001 struct ca0132_spec *spec = codec->spec;
8003 guard(mutex)(&spec->chipio_mutex);
8005 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8006 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8008 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8010 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8011 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8013 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8014 chipio_set_stream_channels(codec, 0x18, 6);
8015 chipio_set_stream_control(codec, 0x18, 1);
8017 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8020 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8031 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8034 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8036 struct ca0132_spec *spec = codec->spec;
8045 guard(mutex)(&spec->chipio_mutex);
8047 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8049 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8050 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8051 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8052 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8054 ae7_post_dsp_pll_setup(codec);
8055 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8058 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8060 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8061 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8062 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8064 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8065 chipio_set_stream_channels(codec, 0x21, 2);
8066 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8068 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8074 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8076 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8082 * know what data is being sent. Interestingly, the AE-5 seems to go
8084 * step, but the AE-7 does.
8087 ca0113_mmio_gpio_set(codec, 0, 1);
8088 ca0113_mmio_gpio_set(codec, 1, 1);
8090 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8091 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8092 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8093 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8095 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8096 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8098 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8099 chipio_set_stream_channels(codec, 0x18, 6);
8105 ae7_post_dsp_pll_setup(codec);
8106 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8114 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8116 chipio_8051_write_direct(codec, 0x93, 0x10);
8118 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8120 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8121 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8123 chipio_set_control_param(codec, 3, 3);
8124 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8127 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8128 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8130 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8132 ae7_post_dsp_pll_setup(codec);
8133 ae7_post_dsp_asi_stream_setup(codec);
8135 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8137 ae7_post_dsp_asi_setup_ports(codec);
8143 static void ca0132_setup_defaults(struct hda_codec *codec)
8145 struct ca0132_spec *spec = codec->spec;
8150 if (spec->dsp_state != DSP_DOWNLOADED)
8154 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8157 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8165 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8168 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8172 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8173 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8177 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8181 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8188 static void r3d_setup_defaults(struct hda_codec *codec)
8190 struct ca0132_spec *spec = codec->spec;
8195 if (spec->dsp_state != DSP_DOWNLOADED)
8198 ca0132_alt_init_analog_mics(codec);
8199 ca0132_alt_start_dsp_audio_streams(codec);
8203 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8207 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8208 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8211 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8214 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8218 ca0113_mmio_gpio_set(codec, 2, false);
8219 ca0113_mmio_gpio_set(codec, 4, true);
8223 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8226 dspio_set_uint_param(codec,
8238 static void sbz_setup_defaults(struct hda_codec *codec)
8240 struct ca0132_spec *spec = codec->spec;
8245 if (spec->dsp_state != DSP_DOWNLOADED)
8248 ca0132_alt_init_analog_mics(codec);
8249 ca0132_alt_start_dsp_audio_streams(codec);
8250 sbz_connect_streams(codec);
8251 sbz_chipio_startup_data(codec);
8258 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8259 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8263 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8267 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8268 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8271 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8273 ca0132_alt_dsp_initial_mic_setup(codec);
8276 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8279 dspio_set_uint_param(codec,
8286 ca0132_alt_init_speaker_tuning(codec);
8290 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8292 static void ae5_setup_defaults(struct hda_codec *codec)
8294 struct ca0132_spec *spec = codec->spec;
8299 if (spec->dsp_state != DSP_DOWNLOADED)
8302 ca0132_alt_init_analog_mics(codec);
8303 ca0132_alt_start_dsp_audio_streams(codec);
8307 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8308 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8309 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8310 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8312 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8313 ca0113_mmio_gpio_set(codec, 0, false);
8314 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8318 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8319 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8323 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8327 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8328 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8331 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8333 ca0132_alt_dsp_initial_mic_setup(codec);
8334 ae5_post_dsp_register_set(codec);
8335 ae5_post_dsp_param_setup(codec);
8336 ae5_post_dsp_pll_setup(codec);
8337 ae5_post_dsp_stream_setup(codec);
8338 ae5_post_dsp_startup_data(codec);
8341 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8344 dspio_set_uint_param(codec,
8351 ca0132_alt_init_speaker_tuning(codec);
8355 * Setup default parameters for the Sound Blaster AE-7 DSP.
8357 static void ae7_setup_defaults(struct hda_codec *codec)
8359 struct ca0132_spec *spec = codec->spec;
8364 if (spec->dsp_state != DSP_DOWNLOADED)
8367 ca0132_alt_init_analog_mics(codec);
8368 ca0132_alt_start_dsp_audio_streams(codec);
8369 ae7_post_dsp_setup_ports(codec);
8372 dspio_set_uint_param(codec, 0x96,
8374 dspio_set_uint_param(codec, 0x96,
8377 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8380 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8381 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8383 ca0113_mmio_gpio_set(codec, 0, false);
8387 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8388 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8392 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8396 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8397 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8400 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8401 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8407 ca0132_alt_init_analog_mics(codec);
8409 ae7_post_dsp_asi_setup(codec);
8412 * Not sure why, but these are both set to 1. They're only set to 0
8415 ca0113_mmio_gpio_set(codec, 0, true);
8416 ca0113_mmio_gpio_set(codec, 1, true);
8419 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8420 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8421 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8424 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8427 dspio_set_uint_param(codec,
8434 ca0132_alt_init_speaker_tuning(codec);
8440 static void ca0132_init_flags(struct hda_codec *codec)
8442 struct ca0132_spec *spec = codec->spec;
8445 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8446 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8447 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8448 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8449 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8450 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8451 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8452 chipio_set_control_flag(codec,
8454 chipio_set_control_flag(codec,
8455 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8457 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8458 chipio_set_control_flag(codec,
8460 chipio_set_control_flag(codec,
8462 chipio_set_control_flag(codec,
8464 chipio_set_control_flag(codec,
8466 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8473 static void ca0132_init_params(struct hda_codec *codec)
8475 struct ca0132_spec *spec = codec->spec;
8478 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8479 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8480 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8481 chipio_set_control_param(codec, 0, 0);
8482 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8485 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8486 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8489 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8491 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8492 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8493 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8494 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8495 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8496 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8498 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8499 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8500 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8503 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8506 struct ca0132_spec *spec = codec->spec;
8519 codec->card->dev) != 0)
8520 codec_dbg(codec, "Desktop firmware not found.");
8522 codec_dbg(codec, "Desktop firmware selected.");
8526 codec->card->dev) != 0)
8527 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8529 codec_dbg(codec, "Recon3Di firmware selected.");
8536 * exists for your particular codec.
8539 codec_dbg(codec, "Default firmware selected.");
8541 codec->card->dev) != 0)
8545 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8546 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8547 codec_err(codec, "ca0132 DSP load image failed\n");
8551 dsp_loaded = dspload_wait_loaded(codec);
8559 static void ca0132_download_dsp(struct hda_codec *codec)
8561 struct ca0132_spec *spec = codec->spec;
8567 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8570 chipio_enable_clocks(codec);
8571 if (spec->dsp_state != DSP_DOWNLOADED) {
8572 spec->dsp_state = DSP_DOWNLOADING;
8574 if (!ca0132_download_dsp_images(codec))
8575 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8577 spec->dsp_state = DSP_DOWNLOADED;
8581 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8582 ca0132_set_dsp_msr(codec, true);
8585 static void ca0132_process_dsp_response(struct hda_codec *codec,
8588 struct ca0132_spec *spec = codec->spec;
8590 codec_dbg(codec, "ca0132_process_dsp_response\n");
8591 CLASS(snd_hda_power_pm, pm)(codec);
8592 if (spec->wait_scp) {
8593 if (dspio_get_response_data(codec) >= 0)
8594 spec->wait_scp = 0;
8597 dspio_clear_response_queue(codec);
8600 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8602 struct ca0132_spec *spec = codec->spec;
8605 /* Delay enabling the HP amp, to let the mic-detection
8608 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8610 tbl->block_report = 1;
8611 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8614 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8616 struct ca0132_spec *spec = codec->spec;
8619 ca0132_alt_select_in(codec);
8621 ca0132_select_mic(codec);
8624 static void ca0132_setup_unsol(struct hda_codec *codec)
8626 struct ca0132_spec *spec = codec->spec;
8627 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8628 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8630 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8634 snd_hda_jack_detect_enable_callback(codec,
8635 spec->unsol_tag_front_hp, hp_callback);
8713 static void ca0132_init_chip(struct hda_codec *codec)
8715 struct ca0132_spec *spec = codec->spec;
8720 mutex_init(&spec->chipio_mutex);
8729 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8730 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8732 snd_hda_codec_write(codec, codec->core.afg, 0,
8734 snd_hda_codec_write(codec, codec->core.afg, 0,
8738 spec->cur_out_type = SPEAKER_OUT;
8740 spec->cur_mic_type = DIGITAL_MIC;
8742 spec->cur_mic_type = REAR_MIC;
8744 spec->cur_mic_boost = 0;
8747 spec->vnode_lvol[i] = 0x5a;
8748 spec->vnode_rvol[i] = 0x5a;
8749 spec->vnode_lswitch[i] = 0;
8750 spec->vnode_rswitch[i] = 0;
8759 spec->effects_switch[i] = on ? 1 : 0;
8763 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8767 spec->speaker_range_val[0] = 1;
8768 spec->speaker_range_val[1] = 1;
8770 spec->xbass_xover_freq = 8;
8772 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8774 spec->bass_redirect_xover_freq = 8;
8777 spec->voicefx_val = 0;
8778 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8779 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8782 * The ZxR doesn't have a front panel header, and it's line-in is on
8784 * to make sure that spec->in_enum_val is set properly.
8787 spec->in_enum_val = REAR_MIC;
8790 ca0132_init_tuning_defaults(codec);
8798 static void r3di_gpio_shutdown(struct hda_codec *codec)
8800 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8806 static void sbz_region2_exit(struct hda_codec *codec)
8808 struct ca0132_spec *spec = codec->spec;
8812 writeb(0x0, spec->mem_base + 0x100);
8814 writeb(0xb3, spec->mem_base + 0x304);
8816 ca0113_mmio_gpio_set(codec, 0, false);
8817 ca0113_mmio_gpio_set(codec, 1, false);
8818 ca0113_mmio_gpio_set(codec, 4, true);
8819 ca0113_mmio_gpio_set(codec, 5, false);
8820 ca0113_mmio_gpio_set(codec, 7, false);
8823 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8828 snd_hda_codec_write(codec, 0x11, 0,
8832 snd_hda_codec_write(codec, pins[i], 0,
8836 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8842 snd_hda_codec_write(codec, pins[i], 0,
8848 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8852 snd_hda_codec_write(codec, 0x01, 0,
8855 snd_hda_codec_write(codec, 0x01, 0,
8859 snd_hda_codec_write(codec, 0x01, 0,
8863 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8869 snd_hda_codec_write(codec, pins[i], 0,
8873 static void sbz_exit_chip(struct hda_codec *codec)
8875 chipio_set_stream_control(codec, 0x03, 0);
8876 chipio_set_stream_control(codec, 0x04, 0);
8879 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8880 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8881 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8883 chipio_set_stream_control(codec, 0x14, 0);
8884 chipio_set_stream_control(codec, 0x0C, 0);
8886 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8887 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8889 chipio_write(codec, 0x18a020, 0x00000083);
8891 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8892 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8893 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8895 chipio_set_stream_control(codec, 0x0C, 0);
8897 chipio_set_control_param(codec, 0x0D, 0x24);
8899 ca0132_clear_unsolicited(codec);
8900 sbz_set_pin_ctl_default(codec);
8902 snd_hda_codec_write(codec, 0x0B, 0,
8905 sbz_region2_exit(codec);
8908 static void r3d_exit_chip(struct hda_codec *codec)
8910 ca0132_clear_unsolicited(codec);
8911 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8912 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8915 static void ae5_exit_chip(struct hda_codec *codec)
8917 chipio_set_stream_control(codec, 0x03, 0);
8918 chipio_set_stream_control(codec, 0x04, 0);
8920 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8921 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8922 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8923 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8924 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8925 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8926 ca0113_mmio_gpio_set(codec, 0, false);
8927 ca0113_mmio_gpio_set(codec, 1, false);
8929 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8930 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8932 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8934 chipio_set_stream_control(codec, 0x18, 0);
8935 chipio_set_stream_control(codec, 0x0c, 0);
8937 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8940 static void ae7_exit_chip(struct hda_codec *codec)
8942 chipio_set_stream_control(codec, 0x18, 0);
8943 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8944 chipio_set_stream_channels(codec, 0x21, 0);
8945 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8946 chipio_set_control_param(codec, 0x20, 0x01);
8948 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8950 chipio_set_stream_control(codec, 0x18, 0);
8951 chipio_set_stream_control(codec, 0x0c, 0);
8953 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8954 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8955 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8956 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8957 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8958 ca0113_mmio_gpio_set(codec, 0, false);
8959 ca0113_mmio_gpio_set(codec, 1, false);
8960 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8962 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8963 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8966 static void zxr_exit_chip(struct hda_codec *codec)
8968 chipio_set_stream_control(codec, 0x03, 0);
8969 chipio_set_stream_control(codec, 0x04, 0);
8970 chipio_set_stream_control(codec, 0x14, 0);
8971 chipio_set_stream_control(codec, 0x0C, 0);
8973 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8974 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8976 chipio_write(codec, 0x18a020, 0x00000083);
8978 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8979 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8981 ca0132_clear_unsolicited(codec);
8982 sbz_set_pin_ctl_default(codec);
8983 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8985 ca0113_mmio_gpio_set(codec, 5, false);
8986 ca0113_mmio_gpio_set(codec, 2, false);
8987 ca0113_mmio_gpio_set(codec, 3, false);
8988 ca0113_mmio_gpio_set(codec, 0, false);
8989 ca0113_mmio_gpio_set(codec, 4, true);
8990 ca0113_mmio_gpio_set(codec, 0, true);
8991 ca0113_mmio_gpio_set(codec, 5, true);
8992 ca0113_mmio_gpio_set(codec, 2, false);
8993 ca0113_mmio_gpio_set(codec, 3, false);
8996 static void ca0132_exit_chip(struct hda_codec *codec)
9000 if (dspload_is_loaded(codec))
9001 dsp_reset(codec);
9012 static void sbz_dsp_startup_check(struct hda_codec *codec)
9014 struct ca0132_spec *spec = codec->spec;
9021 if (spec->startup_check_entered)
9024 spec->startup_check_entered = true;
9027 chipio_read(codec, cur_address, &dsp_data_check[i]);
9032 failure = 1;
9035 codec_dbg(codec, "Startup Check: %d ", failure);
9037 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9044 codec_info(codec, "Reloading... Tries left: %d", reload);
9045 sbz_exit_chip(codec);
9046 spec->dsp_state = DSP_DOWNLOAD_INIT;
9047 snd_hda_codec_init(codec);
9050 chipio_read(codec, cur_address, &dsp_data_check[i]);
9055 failure = 1;
9057 reload--;
9061 codec_info(codec, "DSP fixed.");
9066 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9077 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9079 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9080 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9081 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9082 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9083 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9084 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9085 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9086 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9092 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9094 struct ca0132_spec *spec = codec->spec;
9096 writel(0x00820680, spec->mem_base + 0x01C);
9097 writel(0x00820680, spec->mem_base + 0x01C);
9099 chipio_write(codec, 0x18b0a4, 0x000000c2);
9101 snd_hda_codec_write(codec, 0x11, 0,
9105 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9107 chipio_write(codec, 0x18b0a4, 0x000000c2);
9109 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9111 snd_hda_codec_write(codec, 0x11, 0,
9115 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9117 chipio_write(codec, 0x18b0a4, 0x000000c2);
9119 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9120 chipio_8051_write_exram(codec, 0x1920, 0x00);
9121 chipio_8051_write_exram(codec, 0x1921, 0x40);
9123 snd_hda_codec_write(codec, 0x11, 0,
9132 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9138 chipio_write(codec, 0x189000, 0x0001f100);
9140 chipio_write(codec, 0x18900c, 0x0001f100);
9149 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9151 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9154 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9156 chipio_write(codec, 0x18902c, 0x00000000);
9158 chipio_write(codec, 0x18902c, 0x00000003);
9162 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9205 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9207 struct ca0132_spec *spec = codec->spec;
9213 writel(0x00000000, spec->mem_base + addr[i]);
9219 tmp[1] = 0x00000080;
9223 tmp[1] = 0x00000083;
9227 tmp[1] = 0x00000083;
9231 tmp[1] = 0x00000000;
9236 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9252 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9255 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9257 struct ca0132_spec *spec = codec->spec;
9266 writel(0x00000680, spec->mem_base + 0x1c);
9267 writel(0x00880680, spec->mem_base + 0x1c);
9272 * AE-7 shares all writes with the AE-5, except that it writes
9276 writel(0x00800001, spec->mem_base + addr[i]);
9280 writel(data[i], spec->mem_base + addr[i]);
9284 writel(0x00880680, spec->mem_base + 0x1c);
9287 static void ca0132_mmio_init(struct hda_codec *codec)
9289 struct ca0132_spec *spec = codec->spec;
9295 ca0132_mmio_init_sbz(codec);
9298 ca0132_mmio_init_ae5(codec);
9317 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9320 static void ae5_register_set(struct hda_codec *codec)
9322 struct ca0132_spec *spec = codec->spec;
9330 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9332 chipio_8051_write_direct(codec, 0x93, 0x10);
9333 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9337 tmp[1] = 0x03;
9341 tmp[1] = 0x0f;
9346 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9353 writeb(data[i], spec->mem_base + addr[cur_addr]);
9356 writel(data[i], spec->mem_base + addr[cur_addr]);
9358 writel(0x00800001, spec->mem_base + 0x20c);
9361 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9362 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9364 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9367 chipio_8051_write_direct(codec, 0x90, 0x00);
9368 chipio_8051_write_direct(codec, 0x90, 0x10);
9371 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9379 static void ca0132_alt_init(struct hda_codec *codec)
9381 struct ca0132_spec *spec = codec->spec;
9383 ca0132_alt_vol_setup(codec);
9387 codec_dbg(codec, "SBZ alt_init");
9388 ca0132_gpio_init(codec);
9389 sbz_pre_dsp_setup(codec);
9390 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9391 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9394 codec_dbg(codec, "R3DI alt_init");
9395 ca0132_gpio_init(codec);
9396 ca0132_gpio_setup(codec);
9397 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9398 r3di_pre_dsp_setup(codec);
9399 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9403 r3d_pre_dsp_setup(codec);
9404 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9405 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9408 ca0132_gpio_init(codec);
9409 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9410 chipio_write(codec, 0x18b030, 0x00000020);
9411 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9412 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9413 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9416 ca0132_gpio_init(codec);
9417 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9418 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9419 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9420 chipio_write(codec, 0x18b008, 0x000000f8);
9421 chipio_write(codec, 0x18b008, 0x000000f0);
9422 chipio_write(codec, 0x18b030, 0x00000020);
9423 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9426 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9427 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9428 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9429 zxr_pre_dsp_setup(codec);
9436 static int ca0132_init(struct hda_codec *codec)
9438 struct ca0132_spec *spec = codec->spec;
9439 struct auto_pin_cfg *cfg = &spec->autocfg;
9445 * there's only two reasons for it. One, the codec has awaken from a
9453 if (spec->dsp_state == DSP_DOWNLOADED) {
9454 dsp_loaded = dspload_is_loaded(codec);
9456 spec->dsp_reload = true;
9457 spec->dsp_state = DSP_DOWNLOAD_INIT;
9460 sbz_dsp_startup_check(codec);
9465 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9466 spec->dsp_state = DSP_DOWNLOAD_INIT;
9467 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9470 ca0132_mmio_init(codec);
9472 CLASS(snd_hda_power_pm, pm)(codec);
9475 ae5_register_set(codec);
9477 ca0132_init_params(codec);
9478 ca0132_init_flags(codec);
9480 snd_hda_sequence_write(codec, spec->base_init_verbs);
9483 ca0132_alt_init(codec);
9485 ca0132_download_dsp(codec);
9487 ca0132_refresh_widget_caps(codec);
9492 r3d_setup_defaults(codec);
9496 sbz_setup_defaults(codec);
9499 ae5_setup_defaults(codec);
9502 ae7_setup_defaults(codec);
9505 ca0132_setup_defaults(codec);
9506 ca0132_init_analog_mic2(codec);
9507 ca0132_init_dmic(codec);
9511 for (i = 0; i < spec->num_outputs; i++)
9512 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9514 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9516 for (i = 0; i < spec->num_inputs; i++)
9517 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9519 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9522 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9523 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9525 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9530 ca0132_gpio_setup(codec);
9532 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9534 ca0132_alt_select_out(codec);
9535 ca0132_alt_select_in(codec);
9537 ca0132_select_out(codec);
9538 ca0132_select_mic(codec);
9541 snd_hda_jack_report_sync(codec);
9547 if (spec->dsp_reload) {
9548 spec->dsp_reload = false;
9549 ca0132_pe_switch_set(codec);
9555 static int dbpro_init(struct hda_codec *codec)
9557 struct ca0132_spec *spec = codec->spec;
9558 struct auto_pin_cfg *cfg = &spec->autocfg;
9561 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9562 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9564 for (i = 0; i < spec->num_inputs; i++)
9565 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9570 static void ca0132_free(struct hda_codec *codec)
9572 struct ca0132_spec *spec = codec->spec;
9574 cancel_delayed_work_sync(&spec->unsol_hp_work);
9575 snd_hda_power_up(codec);
9578 sbz_exit_chip(codec);
9581 zxr_exit_chip(codec);
9584 r3d_exit_chip(codec);
9587 ae5_exit_chip(codec);
9590 ae7_exit_chip(codec);
9593 r3di_gpio_shutdown(codec);
9599 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9600 ca0132_exit_chip(codec);
9602 snd_hda_power_down(codec);
9604 if (spec->mem_base)
9605 pci_iounmap(codec->bus->pci, spec->mem_base);
9607 kfree(spec->spec_init_verbs);
9608 kfree(codec->spec);
9611 static void dbpro_free(struct hda_codec *codec)
9613 struct ca0132_spec *spec = codec->spec;
9615 zxr_dbpro_power_state_shutdown(codec);
9617 kfree(spec->spec_init_verbs);
9618 kfree(codec->spec);
9621 static void ca0132_config(struct hda_codec *codec)
9623 struct ca0132_spec *spec = codec->spec;
9625 spec->dacs[0] = 0x2;
9626 spec->dacs[1] = 0x3;
9627 spec->dacs[2] = 0x4;
9629 spec->multiout.dac_nids = spec->dacs;
9630 spec->multiout.num_dacs = 3;
9633 spec->multiout.max_channels = 2;
9635 spec->multiout.max_channels = 6;
9639 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9640 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9643 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9644 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9647 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9648 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9651 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9652 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9655 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9656 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9659 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9660 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9663 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9664 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9672 spec->num_outputs = 2;
9673 spec->out_pins[0] = 0x0b; /* speaker out */
9674 spec->out_pins[1] = 0x0f;
9675 spec->shared_out_nid = 0x2;
9676 spec->unsol_tag_hp = 0x0f;
9678 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9679 spec->adcs[1] = 0x8; /* analog mic2 */
9680 spec->adcs[2] = 0xa; /* what u hear */
9682 spec->num_inputs = 3;
9683 spec->input_pins[0] = 0x12;
9684 spec->input_pins[1] = 0x11;
9685 spec->input_pins[2] = 0x13;
9686 spec->shared_mic_nid = 0x7;
9687 spec->unsol_tag_amic1 = 0x11;
9691 spec->num_outputs = 2;
9692 spec->out_pins[0] = 0x0B; /* Line out */
9693 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9694 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9695 spec->out_pins[3] = 0x11; /* Rear surround */
9696 spec->shared_out_nid = 0x2;
9697 spec->unsol_tag_hp = spec->out_pins[1];
9698 spec->unsol_tag_front_hp = spec->out_pins[2];
9700 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9701 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9702 spec->adcs[2] = 0xa; /* what u hear */
9704 spec->num_inputs = 2;
9705 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9706 spec->input_pins[1] = 0x13; /* What U Hear */
9707 spec->shared_mic_nid = 0x7;
9708 spec->unsol_tag_amic1 = spec->input_pins[0];
9711 spec->dig_out = 0x05;
9712 spec->multiout.dig_out_nid = spec->dig_out;
9713 spec->dig_in = 0x09;
9716 spec->num_outputs = 2;
9717 spec->out_pins[0] = 0x0B; /* Line out */
9718 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9719 spec->out_pins[2] = 0x10; /* Center/LFE */
9720 spec->out_pins[3] = 0x11; /* Rear surround */
9721 spec->shared_out_nid = 0x2;
9722 spec->unsol_tag_hp = spec->out_pins[1];
9723 spec->unsol_tag_front_hp = spec->out_pins[2];
9725 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9726 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9727 spec->adcs[2] = 0xa; /* what u hear */
9729 spec->num_inputs = 2;
9730 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9731 spec->input_pins[1] = 0x13; /* What U Hear */
9732 spec->shared_mic_nid = 0x7;
9733 spec->unsol_tag_amic1 = spec->input_pins[0];
9736 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9738 spec->num_inputs = 1;
9739 spec->input_pins[0] = 0x11; /* RCA Line-in */
9741 spec->dig_out = 0x05;
9742 spec->multiout.dig_out_nid = spec->dig_out;
9744 spec->dig_in = 0x09;
9748 spec->num_outputs = 2;
9749 spec->out_pins[0] = 0x0B; /* Line out */
9750 spec->out_pins[1] = 0x11; /* Rear headphone out */
9751 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9752 spec->out_pins[3] = 0x0F; /* Rear surround */
9753 spec->shared_out_nid = 0x2;
9754 spec->unsol_tag_hp = spec->out_pins[1];
9755 spec->unsol_tag_front_hp = spec->out_pins[2];
9757 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9758 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9759 spec->adcs[2] = 0xa; /* what u hear */
9761 spec->num_inputs = 2;
9762 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9763 spec->input_pins[1] = 0x13; /* What U Hear */
9764 spec->shared_mic_nid = 0x7;
9765 spec->unsol_tag_amic1 = spec->input_pins[0];
9768 spec->dig_out = 0x05;
9769 spec->multiout.dig_out_nid = spec->dig_out;
9772 spec->num_outputs = 2;
9773 spec->out_pins[0] = 0x0B; /* Line out */
9774 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9775 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9776 spec->out_pins[3] = 0x11; /* Rear surround */
9777 spec->shared_out_nid = 0x2;
9778 spec->unsol_tag_hp = spec->out_pins[1];
9779 spec->unsol_tag_front_hp = spec->out_pins[2];
9781 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9782 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9783 spec->adcs[2] = 0x0a; /* what u hear */
9785 spec->num_inputs = 2;
9786 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9787 spec->input_pins[1] = 0x13; /* What U Hear */
9788 spec->shared_mic_nid = 0x7;
9789 spec->unsol_tag_amic1 = spec->input_pins[0];
9792 spec->dig_out = 0x05;
9793 spec->multiout.dig_out_nid = spec->dig_out;
9796 spec->num_outputs = 2;
9797 spec->out_pins[0] = 0x0b; /* speaker out */
9798 spec->out_pins[1] = 0x10; /* headphone out */
9799 spec->shared_out_nid = 0x2;
9800 spec->unsol_tag_hp = spec->out_pins[1];
9802 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9803 spec->adcs[1] = 0x8; /* analog mic2 */
9804 spec->adcs[2] = 0xa; /* what u hear */
9806 spec->num_inputs = 3;
9807 spec->input_pins[0] = 0x12;
9808 spec->input_pins[1] = 0x11;
9809 spec->input_pins[2] = 0x13;
9810 spec->shared_mic_nid = 0x7;
9811 spec->unsol_tag_amic1 = spec->input_pins[0];
9814 spec->dig_out = 0x05;
9815 spec->multiout.dig_out_nid = spec->dig_out;
9816 spec->dig_in = 0x09;
9821 static int ca0132_prepare_verbs(struct hda_codec *codec)
9825 struct ca0132_spec *spec = codec->spec;
9827 spec->chip_init_verbs = ca0132_init_verbs0;
9833 spec->desktop_init_verbs = ca0132_init_verbs1;
9834 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9837 if (!spec->spec_init_verbs)
9838 return -ENOMEM;
9841 spec->spec_init_verbs[0].nid = 0x0b;
9842 spec->spec_init_verbs[0].param = 0x78D;
9843 spec->spec_init_verbs[0].verb = 0x00;
9847 spec->spec_init_verbs[2].nid = 0x0b;
9848 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9849 spec->spec_init_verbs[2].verb = 0x02;
9851 spec->spec_init_verbs[3].nid = 0x10;
9852 spec->spec_init_verbs[3].param = 0x78D;
9853 spec->spec_init_verbs[3].verb = 0x02;
9855 spec->spec_init_verbs[4].nid = 0x10;
9856 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9857 spec->spec_init_verbs[4].verb = 0x02;
9860 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9866 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9870 static void sbz_detect_quirk(struct hda_codec *codec)
9872 switch (codec->core.subsystem_id) {
9874 codec->fixup_id = QUIRK_ZXR;
9877 codec->fixup_id = QUIRK_ZXR_DBPRO;
9880 codec->fixup_id = QUIRK_SBZ;
9885 static void ca0132_codec_remove(struct hda_codec *codec)
9887 struct ca0132_spec *spec = codec->spec;
9890 return dbpro_free(codec);
9892 return ca0132_free(codec);
9895 static int ca0132_codec_probe(struct hda_codec *codec,
9901 codec_dbg(codec, "%s\n", __func__);
9905 return -ENOMEM;
9906 codec->spec = spec;
9907 spec->codec = codec;
9909 /* Detect codec quirk */
9910 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL);
9912 sbz_detect_quirk(codec);
9914 codec->pcm_format_first = 1;
9915 codec->no_sticky_stream = 1;
9918 spec->dsp_state = DSP_DOWNLOAD_INIT;
9919 spec->num_mixers = 1;
9924 spec->mixers[0] = desktop_mixer;
9925 snd_hda_codec_set_name(codec, "Sound Blaster Z");
9928 spec->mixers[0] = desktop_mixer;
9929 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9934 spec->mixers[0] = desktop_mixer;
9935 snd_hda_codec_set_name(codec, "Recon3D");
9938 spec->mixers[0] = r3di_mixer;
9939 snd_hda_codec_set_name(codec, "Recon3Di");
9942 spec->mixers[0] = desktop_mixer;
9943 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9946 spec->mixers[0] = desktop_mixer;
9947 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9950 spec->mixers[0] = ca0132_mixer;
9961 spec->use_alt_controls = true;
9962 spec->use_alt_functions = true;
9963 spec->use_pci_mmio = true;
9966 spec->use_alt_controls = true;
9967 spec->use_alt_functions = true;
9968 spec->use_pci_mmio = false;
9971 spec->use_alt_controls = false;
9972 spec->use_alt_functions = false;
9973 spec->use_pci_mmio = false;
9978 if (spec->use_pci_mmio) {
9979 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9980 if (spec->mem_base == NULL) {
9981 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9982 codec->fixup_id = QUIRK_NONE;
9987 spec->base_init_verbs = ca0132_base_init_verbs;
9988 spec->base_exit_verbs = ca0132_base_exit_verbs;
9990 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9992 ca0132_init_chip(codec);
9994 ca0132_config(codec);
9996 err = ca0132_prepare_verbs(codec);
10000 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10004 ca0132_setup_unsol(codec);
10009 ca0132_codec_remove(codec);
10013 static int ca0132_codec_build_controls(struct hda_codec *codec)
10015 struct ca0132_spec *spec = codec->spec;
10018 return dbpro_build_controls(codec);
10020 return ca0132_build_controls(codec);
10023 static int ca0132_codec_build_pcms(struct hda_codec *codec)
10025 struct ca0132_spec *spec = codec->spec;
10028 return dbpro_build_pcms(codec);
10030 return ca0132_build_pcms(codec);
10033 static int ca0132_codec_init(struct hda_codec *codec)
10035 struct ca0132_spec *spec = codec->spec;
10038 return dbpro_init(codec);
10040 return ca0132_init(codec);
10043 static int ca0132_codec_suspend(struct hda_codec *codec)
10045 struct ca0132_spec *spec = codec->spec;
10047 cancel_delayed_work_sync(&spec->unsol_hp_work);
10071 MODULE_DESCRIPTION("Creative Sound Core3D codec");