Lines Matching +full:codec +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HD audio codec driver for Creative CA0132 chip
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x80
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
70 #define SCP_SET 0
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
107 #define VNODE_START_NID 0x80
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
117 #define EFFECT_START_NID 0x90
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
163 * X-bass.
170 #define DSP_CAPTURE_INIT_LATENCY 0
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
187 #define EFX_DIR_OUT 0
193 .mid = 0x96,
194 .reqs = {0, 1},
197 .def_vals = {0x3F800000, 0x3F2B851F}
201 .mid = 0x96,
205 .def_vals = {0x3F800000, 0x3F266666}
209 .mid = 0x96,
213 .def_vals = {0x00000000, 0x3F000000}
217 .mid = 0x96,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
223 { .name = "X-Bass",
225 .mid = 0x96,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
233 .mid = 0x96,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
252 .mid = 0x95,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
260 .mid = 0x95,
264 .def_vals = {0x00000000, 0x3F3D70A4}
268 .mid = 0x95,
272 .def_vals = {0x3F800000, 0x3F000000}
276 .mid = 0x95,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
290 #define TUNING_CTL_START_NID 0xC0
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
313 int direct; /* 0:output; 1:input*/
321 .mid = 0x95,
324 .def_val = 0x41F00000
329 .mid = 0x95,
332 .def_val = 0x3F3D70A4
337 .mid = 0x96,
340 .def_val = 0x00000000
345 .mid = 0x96,
348 .def_val = 0x00000000
353 .mid = 0x96,
356 .def_val = 0x00000000
361 .mid = 0x96,
364 .def_val = 0x00000000
369 .mid = 0x96,
372 .def_val = 0x00000000
377 .mid = 0x96,
380 .def_val = 0x00000000
385 .mid = 0x96,
388 .def_val = 0x00000000
393 .mid = 0x96,
396 .def_val = 0x00000000
401 .mid = 0x96,
404 .def_val = 0x00000000
409 .mid = 0x96,
412 .def_val = 0x00000000
435 .mid = 0x95,
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
531 .mid = 0x96,
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
604 * enabled. X-Bass must be disabled when using these.
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
619 * module ID 0x96, the output effects module.
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
709 #define DSP_VOL_OUT 0
720 .mid = 0x32,
724 .mid = 0x37,
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
781 .val = 0xa0
784 .val = 0xc0
787 .val = 0x80
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
895 CONTROL_FLAG_C_MGR = 0,
900 /* Tracker for the SPDIF-in path is bypassed/enabled */
918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
920 /* De-emphasis filter on DAC-1 disabled/enabled */
922 /* De-emphasis filter on DAC-2 disabled/enabled */
924 /* De-emphasis filter on DAC-3 disabled/enabled */
926 /* High-pass filter on ADC_B disabled/enabled */
928 /* High-pass filter on ADC_C disabled/enabled */
952 /* 0: None, 1: Mic1In*/
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
965 * sense given the fact the AE-5 uses it and has the ASI flag set.
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1040 SR_COUNT = 0x10,
1042 SR_RATE_UNKNOWN = 0x1F
1046 DSP_DOWNLOAD_FAILED = -1,
1047 DSP_DOWNLOAD_INIT = 0,
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1129 /* AE-5 Control values */
1135 struct hda_codec *codec;
1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id)
1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1194 { 0x0c, 0x411111f0 }, /* N/A */
1195 { 0x0d, 0x411111f0 }, /* N/A */
1196 { 0x0e, 0x411111f0 }, /* N/A */
1197 { 0x0f, 0x0321101f }, /* HP */
1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1199 { 0x11, 0x03a11021 }, /* Mic */
1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1201 { 0x13, 0x411111f0 }, /* N/A */
1202 { 0x18, 0x411111f0 }, /* N/A */
1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1210 { 0x0d, 0x014510f0 }, /* Digital Out */
1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1216 { 0x13, 0x908700f0 }, /* What U Hear In*/
1217 { 0x18, 0x50d000f0 }, /* N/A */
1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1225 { 0x0d, 0x014510f0 }, /* Digital Out */
1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1231 { 0x13, 0x908700f0 }, /* What U Hear In*/
1232 { 0x18, 0x50d000f0 }, /* N/A */
1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1240 { 0x0d, 0x014510f0 }, /* Digital Out */
1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1246 { 0x13, 0x908700f0 }, /* What U Hear In*/
1247 { 0x18, 0x50d000f0 }, /* N/A */
1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1255 { 0x0d, 0x014510f0 }, /* Digital Out */
1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1261 { 0x13, 0x908700f0 }, /* What U Hear In*/
1262 { 0x18, 0x50d000f0 }, /* N/A */
1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1270 { 0x0d, 0x014510f0 }, /* Digital Out */
1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1276 { 0x13, 0x908700f0 }, /* What U Hear In*/
1277 { 0x18, 0x500000f0 }, /* N/A */
1282 { 0x0b, 0x01017010 },
1283 { 0x0c, 0x014510f0 },
1284 { 0x0d, 0x414510f0 },
1285 { 0x0e, 0x01c520f0 },
1286 { 0x0f, 0x01017114 },
1287 { 0x10, 0x01017011 },
1288 { 0x11, 0x018170ff },
1289 { 0x12, 0x01a170f0 },
1290 { 0x13, 0x908700f0 },
1291 { 0x18, 0x500000f0 },
1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" },
1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" },
1335 unsigned int dac2port; /* ParamID 0x0d value. */
1370 { .dac2port = 0x24,
1374 .mmio_gpio_count = 0,
1375 .scp_cmds_count = 0,
1379 { .dac2port = 0x21,
1382 .hda_gpio_set = 0,
1383 .mmio_gpio_count = 0,
1384 .scp_cmds_count = 0,
1393 { .dac2port = 0x24,
1398 .scp_cmds_count = 0,
1402 { .dac2port = 0x21,
1406 .mmio_gpio_set = { 0 },
1407 .scp_cmds_count = 0,
1416 { .dac2port = 0x18,
1420 .mmio_gpio_set = { 0, 1, 1 },
1421 .scp_cmds_count = 0,
1424 { .dac2port = 0x12,
1428 .mmio_gpio_set = { 1, 1, 0 },
1429 .scp_cmds_count = 0,
1438 { .dac2port = 0x24,
1442 .mmio_gpio_set = { 1, 1, 0 },
1443 .scp_cmds_count = 0,
1447 { .dac2port = 0x21,
1451 .mmio_gpio_set = { 0, 1, 1 },
1452 .scp_cmds_count = 0,
1461 { .dac2port = 0xa4,
1463 .mmio_gpio_count = 0,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000012
1474 { .dac2port = 0xa1,
1476 .mmio_gpio_count = 0,
1478 .scp_cmd_mid = { 0x96, 0x96 },
1483 .chipio_write_addr = 0x0018b03c,
1484 .chipio_write_data = 0x00000012
1492 { .dac2port = 0x58,
1495 .mmio_gpio_pin = { 0 },
1498 .scp_cmd_mid = { 0x96, 0x96 },
1503 .chipio_write_addr = 0x0018b03c,
1504 .chipio_write_data = 0x00000000
1507 { .dac2port = 0x58,
1510 .mmio_gpio_pin = { 0 },
1513 .scp_cmd_mid = { 0x96, 0x96 },
1518 .chipio_write_addr = 0x0018b03c,
1519 .chipio_write_data = 0x00000010
1525 * CA0132 codec access
1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1534 return ((response == -1) ? -1 : 0);
1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1541 converter_format & 0xffff, res);
1544 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1548 unsigned char converter_stream_channel = 0;
1550 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1556 static int chipio_send(struct hda_codec *codec,
1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1568 return 0;
1572 return -EIO;
1576 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1578 static int chipio_write_address(struct hda_codec *codec,
1581 struct ca0132_spec *spec = codec->spec;
1584 if (spec->curr_chip_addx == chip_addx)
1585 return 0;
1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1589 chip_addx & 0xffff);
1591 if (res != -EIO) {
1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1603 * Write data through the vendor widget -- NOT protected by the Mutex!
1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1607 struct ca0132_spec *spec = codec->spec;
1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1613 if (res != -EIO) {
1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1621 spec->curr_chip_addx = (res != -EIO) ?
1622 (spec->curr_chip_addx + 4) : ~0U;
1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1629 static int chipio_write_data_multiple(struct hda_codec *codec,
1633 int status = 0;
1636 codec_dbg(codec, "chipio_write_data null ptr\n");
1637 return -EINVAL;
1640 while ((count-- != 0) && (status == 0))
1641 status = chipio_write_data(codec, *data++);
1648 * Read data through the vendor widget -- NOT protected by the Mutex!
1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1652 struct ca0132_spec *spec = codec->spec;
1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1658 if (res != -EIO) {
1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1663 if (res != -EIO) {
1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1667 0);
1672 spec->curr_chip_addx = (res != -EIO) ?
1673 (spec->curr_chip_addx + 4) : ~0U;
1681 static int chipio_write(struct hda_codec *codec,
1684 struct ca0132_spec *spec = codec->spec;
1687 guard(mutex)(&spec->chipio_mutex);
1690 err = chipio_write_address(codec, chip_addx);
1691 if (err < 0)
1694 return chipio_write_data(codec, data);
1701 static int chipio_write_no_mutex(struct hda_codec *codec,
1708 err = chipio_write_address(codec, chip_addx);
1709 if (err < 0)
1712 err = chipio_write_data(codec, data);
1713 if (err < 0)
1724 static int chipio_write_multiple(struct hda_codec *codec,
1729 struct ca0132_spec *spec = codec->spec;
1732 guard(mutex)(&spec->chipio_mutex);
1733 status = chipio_write_address(codec, chip_addx);
1734 if (status < 0)
1737 return chipio_write_data_multiple(codec, data, count);
1744 static int chipio_read(struct hda_codec *codec,
1747 struct ca0132_spec *spec = codec->spec;
1750 guard(mutex)(&spec->chipio_mutex);
1753 err = chipio_write_address(codec, chip_addx);
1754 if (err < 0)
1757 return chipio_read_data(codec, data);
1763 static void chipio_set_control_flag(struct hda_codec *codec,
1770 flag_bit = (flag_state ? 1 : 0);
1772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1779 static void chipio_set_control_param(struct hda_codec *codec,
1782 struct ca0132_spec *spec = codec->spec;
1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790 guard(mutex)(&spec->chipio_mutex);
1791 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1805 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1812 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1815 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1819 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1829 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1832 chipio_set_control_param_no_mutex(codec,
1834 chipio_set_control_param_no_mutex(codec,
1836 chipio_set_control_param_no_mutex(codec,
1843 static void chipio_set_stream_channels(struct hda_codec *codec,
1846 chipio_set_control_param_no_mutex(codec,
1848 chipio_set_control_param_no_mutex(codec,
1855 static void chipio_set_stream_control(struct hda_codec *codec,
1858 chipio_set_control_param_no_mutex(codec,
1860 chipio_set_control_param_no_mutex(codec,
1867 static void chipio_get_stream_control(struct hda_codec *codec,
1870 chipio_set_control_param_no_mutex(codec,
1872 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1880 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1883 chipio_set_control_param_no_mutex(codec,
1885 chipio_set_control_param_no_mutex(codec,
1892 static void chipio_set_conn_rate(struct hda_codec *codec,
1895 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1896 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1903 * 0x80-0xFF.
1905 static void chipio_8051_write_direct(struct hda_codec *codec,
1911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1915 * Writes to the 8051's exram, which has 16-bits of address space.
1916 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1917 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1919 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1922 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1926 /* Lower 8-bits. */
1927 tmp = addr & 0xff;
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1931 /* Upper 8-bits. */
1932 tmp = (addr >> 8) & 0xff;
1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1937 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1939 /* 8-bits of data. */
1940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1941 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1944 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1946 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1947 VENDOR_CHIPIO_8051_DATA_READ, 0);
1951 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1953 /* 8-bits of data. */
1954 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1955 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1958 static void chipio_8051_write_exram(struct hda_codec *codec,
1961 struct ca0132_spec *spec = codec->spec;
1963 guard(mutex)(&spec->chipio_mutex);
1965 chipio_8051_set_address(codec, addr);
1966 chipio_8051_set_data(codec, data);
1969 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1972 chipio_8051_set_address(codec, addr);
1973 chipio_8051_set_data(codec, data);
1977 static void chipio_8051_read_exram(struct hda_codec *codec,
1980 chipio_8051_set_address(codec, addr);
1981 *data = chipio_8051_get_data(codec);
1984 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1987 struct ca0132_spec *spec = codec->spec;
1989 guard(mutex)(&spec->chipio_mutex);
1991 chipio_8051_set_address(codec, addr & 0xff);
1992 chipio_8051_set_data_pll(codec, data);
1995 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
1998 chipio_8051_set_address(codec, addr & 0xff);
1999 chipio_8051_set_data_pll(codec, data);
2005 static void chipio_enable_clocks(struct hda_codec *codec)
2007 struct ca0132_spec *spec = codec->spec;
2009 guard(mutex)(&spec->chipio_mutex);
2011 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2012 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2013 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2019 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2027 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2028 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2033 return -EIO;
2039 static void dspio_write_wait(struct hda_codec *codec)
2045 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2046 VENDOR_DSPIO_STATUS, 0);
2057 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2059 struct ca0132_spec *spec = codec->spec;
2062 dspio_write_wait(codec);
2064 guard(mutex)(&spec->chipio_mutex);
2065 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2066 scp_data & 0xffff);
2067 if (status < 0)
2070 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2072 if (status < 0)
2076 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2077 VENDOR_DSPIO_STATUS, 0);
2080 -EIO : 0;
2086 static int dspio_write_multiple(struct hda_codec *codec,
2089 int status = 0;
2093 return -EINVAL;
2095 count = 0;
2097 status = dspio_write(codec, *buffer++);
2098 if (status != 0)
2106 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2110 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2111 if (status == -EIO)
2114 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2115 if (status == -EIO ||
2117 return -EIO;
2119 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2120 VENDOR_DSPIO_SCP_READ_DATA, 0);
2122 return 0;
2125 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2128 int status = 0;
2135 return -1;
2137 count = 0;
2139 status = dspio_read(codec, buffer++);
2140 if (status != 0)
2146 if (status == 0) {
2148 status = dspio_read(codec, &dummy);
2149 if (status != 0)
2168 unsigned int header = 0;
2170 header = (data_size & 0x1f) << 27;
2171 header |= (error_flag & 0x01) << 26;
2172 header |= (resp_flag & 0x01) << 25;
2173 header |= (device_flag & 0x01) << 24;
2174 header |= (req & 0x7f) << 17;
2175 header |= (get_flag & 0x01) << 16;
2176 header |= (source_id & 0xff) << 8;
2177 header |= target_id & 0xff;
2193 *data_size = (header >> 27) & 0x1f;
2195 *error_flag = (header >> 26) & 0x01;
2197 *resp_flag = (header >> 25) & 0x01;
2199 *device_flag = (header >> 24) & 0x01;
2201 *req = (header >> 17) & 0x7f;
2203 *get_flag = (header >> 16) & 0x01;
2205 *source_id = (header >> 8) & 0xff;
2207 *target_id = header & 0xff;
2218 static void dspio_clear_response_queue(struct hda_codec *codec)
2221 unsigned int dummy = 0;
2226 status = dspio_read(codec, &dummy);
2227 } while (status == 0 && time_before(jiffies, timeout));
2230 static int dspio_get_response_data(struct hda_codec *codec)
2232 struct ca0132_spec *spec = codec->spec;
2233 unsigned int data = 0;
2236 if (dspio_read(codec, &data) < 0)
2237 return -EIO;
2239 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2240 spec->scp_resp_header = data;
2241 spec->scp_resp_count = data >> 27;
2242 count = spec->wait_num_data;
2243 dspio_read_multiple(codec, spec->scp_resp_data,
2244 &spec->scp_resp_count, count);
2245 return 0;
2248 return -EIO;
2254 static int dspio_send_scp_message(struct hda_codec *codec,
2261 struct ca0132_spec *spec = codec->spec;
2263 unsigned int scp_send_size = 0;
2272 *bytes_returned = 0;
2282 return -EINVAL;
2286 return -EINVAL;
2288 spec->wait_scp_header = *((unsigned int *)send_buf);
2293 spec->wait_scp_header &= 0xffff0000;
2294 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2295 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2296 spec->wait_scp = 1;
2300 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2302 if (status < 0) {
2303 spec->wait_scp = 0;
2309 memset(return_buf, 0, return_buf_size);
2312 } while (spec->wait_scp && time_before(jiffies, timeout));
2314 if (!spec->wait_scp) {
2316 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2317 memcpy(&ret_msg->data, spec->scp_resp_data,
2318 spec->wait_num_data);
2319 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2320 status = 0;
2322 status = -EIO;
2324 spec->wait_scp = 0;
2331 * dspio_scp - Prepare and send the SCP message to DSP
2332 * @codec: the HDA codec
2344 static int dspio_scp(struct hda_codec *codec,
2348 int status = 0;
2354 memset(&scp_send, 0, sizeof(scp_send));
2355 memset(&scp_reply, 0, sizeof(scp_reply));
2357 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2358 return -EINVAL;
2361 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2362 return -EINVAL;
2365 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2366 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2367 return -EINVAL;
2371 0, 0, 0, len/sizeof(unsigned int));
2372 if (data != NULL && len > 0) {
2377 ret_bytes = 0;
2379 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2383 if (status < 0) {
2384 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2396 return 0;
2399 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2403 codec_dbg(codec, "reply too long for buf\n");
2404 return -EINVAL;
2406 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2407 return -EINVAL;
2409 codec_dbg(codec, "NULL reply\n");
2410 return -EINVAL;
2416 codec_dbg(codec, "reply ill-formed or errflag set\n");
2417 return -EIO;
2426 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2429 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2433 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2436 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2443 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2445 int status = 0;
2448 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2449 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2450 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2453 if (status < 0) {
2454 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2458 if ((*dma_chan + 1) == 0) {
2459 codec_dbg(codec, "no free dma channels to allocate\n");
2460 return -EBUSY;
2463 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2464 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2472 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2474 int status = 0;
2475 unsigned int dummy = 0;
2477 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2478 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2480 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2484 if (status < 0) {
2485 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2489 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2497 static int dsp_set_run_state(struct hda_codec *codec)
2503 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2504 if (err < 0)
2510 if (halt_state != 0) {
2513 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2515 if (err < 0)
2520 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2522 if (err < 0)
2526 return 0;
2532 static int dsp_reset(struct hda_codec *codec)
2537 codec_dbg(codec, "dsp_reset\n");
2539 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2540 retry--;
2541 } while (res == -EIO && retry);
2544 codec_dbg(codec, "dsp_reset timeout\n");
2545 return -EIO;
2548 return 0;
2575 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2579 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2582 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2585 static int dsp_dma_setup_common(struct hda_codec *codec,
2591 int status = 0;
2597 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2600 codec_dbg(codec, "dma chan num invalid\n");
2601 return -EINVAL;
2604 if (dsp_is_dma_active(codec, dma_chan)) {
2605 codec_dbg(codec, "dma already active\n");
2606 return -EBUSY;
2612 codec_dbg(codec, "invalid chip addr\n");
2613 return -ENXIO;
2617 active = 0;
2619 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2622 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2625 if (status < 0) {
2626 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2629 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2639 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2640 if (status < 0) {
2641 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2644 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2647 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2650 if (status < 0) {
2651 codec_dbg(codec, "read ACTIVE Reg fail\n");
2654 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2660 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2661 if (status < 0) {
2662 codec_dbg(codec, "write ACTIVE Reg fail\n");
2666 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2668 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2670 if (status < 0) {
2671 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2674 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2676 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2678 if (status < 0) {
2679 codec_dbg(codec, "write IRQCNT Reg fail\n");
2682 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2684 codec_dbg(codec,
2685 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2686 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2690 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2692 return 0;
2696 * Setup the DSP DMA per-transfer-specific registers
2698 static int dsp_dma_setup(struct hda_codec *codec,
2703 int status = 0;
2710 unsigned int dma_cfg = 0;
2711 unsigned int adr_ofs = 0;
2712 unsigned int xfr_cnt = 0;
2713 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2716 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2719 codec_dbg(codec, "count too big\n");
2720 return -EINVAL;
2725 codec_dbg(codec, "invalid chip addr\n");
2726 return -ENXIO;
2729 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2732 incr_field = 0;
2743 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2745 if (status < 0) {
2746 codec_dbg(codec, "write DMACFG Reg fail\n");
2749 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2751 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2752 (code ? 0 : 1));
2754 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2756 if (status < 0) {
2757 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2760 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2762 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2764 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2768 status = chipio_write(codec,
2770 if (status < 0) {
2771 codec_dbg(codec, "write XFRCNT Reg fail\n");
2774 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2776 codec_dbg(codec,
2777 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2778 "ADROFS=0x%x, XFRCNT=0x%x\n",
2781 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2783 return 0;
2789 static int dsp_dma_start(struct hda_codec *codec,
2792 unsigned int reg = 0;
2793 int status = 0;
2795 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2798 status = chipio_read(codec,
2801 if (status < 0) {
2802 codec_dbg(codec, "read CHNLSTART reg fail\n");
2805 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2811 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2813 if (status < 0) {
2814 codec_dbg(codec, "write CHNLSTART reg fail\n");
2817 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2825 static int dsp_dma_stop(struct hda_codec *codec,
2828 unsigned int reg = 0;
2829 int status = 0;
2831 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2834 status = chipio_read(codec,
2837 if (status < 0) {
2838 codec_dbg(codec, "read CHNLSTART reg fail\n");
2841 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2846 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2848 if (status < 0) {
2849 codec_dbg(codec, "write CHNLSTART reg fail\n");
2852 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2858 * dsp_allocate_router_ports - Allocate router ports
2860 * @codec: the HDA codec
2868 static int dsp_allocate_router_ports(struct hda_codec *codec,
2874 int status = 0;
2878 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2879 if (status < 0)
2883 val |= (ports_per_channel - 1) << 4;
2884 val |= num_chans - 1;
2886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2890 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2894 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2895 if (status < 0)
2898 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2899 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2903 return (res < 0) ? res : 0;
2909 static int dsp_free_router_ports(struct hda_codec *codec)
2911 int status = 0;
2913 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2914 if (status < 0)
2917 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2921 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2929 static int dsp_allocate_ports(struct hda_codec *codec,
2935 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2938 codec_dbg(codec, "bad rate multiple\n");
2939 return -EINVAL;
2942 status = dsp_allocate_router_ports(codec, num_chans,
2943 rate_multi, 0, port_map);
2945 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2950 static int dsp_allocate_ports_format(struct hda_codec *codec,
2956 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2961 codec_dbg(codec, "bad rate multiple\n");
2962 return -EINVAL;
2967 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2973 static int dsp_free_ports(struct hda_codec *codec)
2977 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2979 status = dsp_free_router_ports(codec);
2980 if (status < 0) {
2981 codec_dbg(codec, "free router ports fail\n");
2984 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2993 struct hda_codec *codec;
3001 DMA_STATE_STOP = 0,
3005 static int dma_convert_to_hda_format(struct hda_codec *codec,
3017 return 0;
3025 struct hda_codec *codec = dma->codec;
3026 struct ca0132_spec *spec = codec->spec;
3029 if (dma->dmab->area)
3030 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3032 status = snd_hda_codec_load_dsp_prepare(codec,
3033 dma->m_converter_format,
3034 dma->buf_size,
3035 dma->dmab);
3036 if (status < 0)
3038 spec->dsp_stream_id = status;
3039 return 0;
3054 return 0;
3057 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3058 return 0;
3063 return dma->dmab->bytes;
3068 return dma->dmab->area;
3075 memcpy(dma->dmab->area, data, count);
3076 return 0;
3084 *format = dma->m_converter_format;
3089 struct ca0132_spec *spec = dma->codec->spec;
3091 return spec->dsp_stream_id;
3101 static const u32 g_magic_value = 0x4c46584d;
3102 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3106 return p->magic == g_magic_value;
3111 return g_chip_addr_magic_value == p->chip_addr;
3116 return p->count == 0;
3121 return struct_size(p, data, p->count);
3133 #define INVALID_DMA_CHANNEL (~0U)
3140 static int dspxfr_hci_write(struct hda_codec *codec,
3147 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3148 codec_dbg(codec, "hci_write invalid params\n");
3149 return -EINVAL;
3152 count = fls->count;
3153 data = (u32 *)(fls->data);
3155 status = chipio_write(codec, data[0], data[1]);
3156 if (status < 0) {
3157 codec_dbg(codec, "hci_write chipio failed\n");
3160 count -= 2;
3163 return 0;
3167 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3169 * @codec: the HDA codec
3171 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3180 static int dspxfr_one_seg(struct hda_codec *codec,
3188 int status = 0;
3209 return -EINVAL;
3216 codec_dbg(codec, "hci_write\n");
3217 return dspxfr_hci_write(codec, hci_write);
3220 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3221 codec_dbg(codec, "Invalid Params\n");
3222 return -EINVAL;
3225 data = fls->data;
3226 chip_addx = fls->chip_addr;
3227 words_to_write = fls->count;
3230 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3232 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3237 codec_dbg(codec, "Invalid chip_addx Params\n");
3238 return -EINVAL;
3247 codec_dbg(codec, "dma_engine buffer NULL\n");
3248 return -EINVAL;
3252 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3256 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3259 if (hda_frame_size_words == 0) {
3260 codec_dbg(codec, "frmsz zero\n");
3261 return -EINVAL;
3267 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3268 codec_dbg(codec,
3269 "chpadr=0x%08x frmsz=%u nchan=%u "
3275 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3276 return -EINVAL;
3285 words_to_write -= remainder_words;
3287 while (words_to_write != 0) {
3289 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3293 status = dsp_dma_stop(codec, dma_chan, ovly);
3294 if (status < 0)
3296 status = dsp_dma_setup_common(codec, chip_addx,
3298 if (status < 0)
3303 status = dsp_dma_setup(codec, chip_addx,
3305 if (status < 0)
3307 status = dsp_dma_start(codec, dma_chan, ovly);
3308 if (status < 0)
3310 if (!dsp_is_dma_active(codec, dma_chan)) {
3311 codec_dbg(codec, "dspxfr:DMA did not start\n");
3312 return -EIO;
3315 if (status < 0)
3317 if (remainder_words != 0) {
3318 status = chipio_write_multiple(codec,
3322 if (status < 0)
3324 remainder_words = 0;
3327 status = dspxfr_hci_write(codec, hci_write);
3328 if (status < 0)
3335 dma_active = dsp_is_dma_active(codec, dma_chan);
3343 codec_dbg(codec, "+++++ DMA complete\n");
3347 if (status < 0)
3352 words_to_write -= run_size_words;
3355 if (remainder_words != 0) {
3356 status = chipio_write_multiple(codec, chip_addx_remainder,
3364 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3366 * @codec: the HDA codec
3368 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3376 static int dspxfr_image(struct hda_codec *codec,
3383 struct ca0132_spec *spec = codec->spec;
3385 unsigned short hda_format = 0;
3387 unsigned char stream_id = 0;
3393 return -EINVAL;
3397 return -ENOMEM;
3399 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3400 if (!dma_engine->dmab) {
3402 return -ENOMEM;
3405 dma_engine->codec = codec;
3406 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3407 dma_engine->m_converter_format = hda_format;
3408 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3411 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3413 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3416 if (status < 0) {
3417 codec_dbg(codec, "set converter format fail\n");
3421 status = snd_hda_codec_load_dsp_prepare(codec,
3422 dma_engine->m_converter_format,
3423 dma_engine->buf_size,
3424 dma_engine->dmab);
3425 if (status < 0)
3427 spec->dsp_stream_id = status;
3430 status = dspio_alloc_dma_chan(codec, &dma_chan);
3431 if (status < 0) {
3432 codec_dbg(codec, "alloc dmachan fail\n");
3438 port_map_mask = 0;
3439 status = dsp_allocate_ports_format(codec, hda_format,
3441 if (status < 0) {
3442 codec_dbg(codec, "alloc ports fail\n");
3447 status = codec_set_converter_stream_channel(codec,
3448 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3449 if (status < 0) {
3450 codec_dbg(codec, "set stream chan fail\n");
3456 codec_dbg(codec, "FLS check fail\n");
3457 status = -EINVAL;
3460 status = dspxfr_one_seg(codec, fls_data, reloc,
3463 if (status < 0)
3473 if (port_map_mask != 0)
3474 status = dsp_free_ports(codec);
3476 if (status < 0)
3479 status = codec_set_converter_stream_channel(codec,
3480 WIDGET_CHIP_CTRL, 0, 0, &response);
3484 dspio_free_dma_chan(codec, dma_chan);
3486 if (dma_engine->dmab->area)
3487 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3488 kfree(dma_engine->dmab);
3497 static void dspload_post_setup(struct hda_codec *codec)
3499 struct ca0132_spec *spec = codec->spec;
3500 codec_dbg(codec, "---- dspload_post_setup ------\n");
3503 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3504 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3507 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3512 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3514 * @codec: the HDA codec
3517 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3520 * @router_chans: number of audio router channels to be allocated (0 means use
3524 * linear, non-constant sized element array of structures, each of which
3529 static int dspload_image(struct hda_codec *codec,
3536 int status = 0;
3540 codec_dbg(codec, "---- dspload_image begin ------\n");
3541 if (router_chans == 0) {
3557 codec_dbg(codec, "Ready to program DMA\n");
3559 status = dsp_reset(codec);
3561 if (status < 0)
3564 codec_dbg(codec, "dsp_reset() complete\n");
3565 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3568 if (status < 0)
3571 codec_dbg(codec, "dspxfr_image() complete\n");
3573 dspload_post_setup(codec);
3574 status = dsp_set_run_state(codec);
3577 codec_dbg(codec, "LOAD FINISHED\n");
3578 } while (0);
3584 static bool dspload_is_loaded(struct hda_codec *codec)
3586 unsigned int data = 0;
3587 int status = 0;
3589 status = chipio_read(codec, 0x40004, &data);
3590 if ((status < 0) || (data != 1))
3596 #define dspload_is_loaded(codec) false
3599 static bool dspload_wait_loaded(struct hda_codec *codec)
3604 if (dspload_is_loaded(codec)) {
3605 codec_info(codec, "ca0132 DSP downloaded and running\n");
3611 codec_err(codec, "ca0132 failed to download DSP\n");
3616 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3622 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3623 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3626 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3627 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3630 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3633 struct ca0132_spec *spec = codec->spec;
3636 gpio_data = gpio_pin & 0xF;
3637 gpio_data |= ((enable << 8) & 0x100);
3639 writew(gpio_data, spec->mem_base + 0x320);
3643 * Special pci region2 commands that are only used by the AE-5. They follow
3648 * target-id, and value.
3650 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3653 struct ca0132_spec *spec = codec->spec;
3656 writel(0x0000007e, spec->mem_base + 0x210);
3657 readl(spec->mem_base + 0x210);
3658 writel(0x0000005a, spec->mem_base + 0x210);
3659 readl(spec->mem_base + 0x210);
3660 readl(spec->mem_base + 0x210);
3662 writel(0x00800005, spec->mem_base + 0x20c);
3663 writel(group, spec->mem_base + 0x804);
3665 writel(0x00800005, spec->mem_base + 0x20c);
3666 write_val = (target & 0xff);
3670 writel(write_val, spec->mem_base + 0x204);
3676 readl(spec->mem_base + 0x860);
3677 readl(spec->mem_base + 0x854);
3678 readl(spec->mem_base + 0x840);
3680 writel(0x00800004, spec->mem_base + 0x20c);
3681 writel(0x00000000, spec->mem_base + 0x210);
3682 readl(spec->mem_base + 0x210);
3683 readl(spec->mem_base + 0x210);
3689 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3692 struct ca0132_spec *spec = codec->spec;
3695 writel(0x0000007e, spec->mem_base + 0x210);
3696 readl(spec->mem_base + 0x210);
3697 writel(0x0000005a, spec->mem_base + 0x210);
3698 readl(spec->mem_base + 0x210);
3699 readl(spec->mem_base + 0x210);
3701 writel(0x00800003, spec->mem_base + 0x20c);
3702 writel(group, spec->mem_base + 0x804);
3704 writel(0x00800005, spec->mem_base + 0x20c);
3705 write_val = (target & 0xff);
3709 writel(write_val, spec->mem_base + 0x204);
3711 readl(spec->mem_base + 0x860);
3712 readl(spec->mem_base + 0x854);
3713 readl(spec->mem_base + 0x840);
3715 writel(0x00800004, spec->mem_base + 0x20c);
3716 writel(0x00000000, spec->mem_base + 0x210);
3717 readl(spec->mem_base + 0x210);
3718 readl(spec->mem_base + 0x210);
3729 static void ca0132_gpio_init(struct hda_codec *codec)
3731 struct ca0132_spec *spec = codec->spec;
3737 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3738 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3739 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3742 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3743 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3752 static void ca0132_gpio_setup(struct hda_codec *codec)
3754 struct ca0132_spec *spec = codec->spec;
3758 snd_hda_codec_write(codec, 0x01, 0,
3759 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3760 snd_hda_codec_write(codec, 0x01, 0,
3761 AC_VERB_SET_GPIO_MASK, 0x07);
3762 snd_hda_codec_write(codec, 0x01, 0,
3763 AC_VERB_SET_GPIO_DATA, 0x04);
3764 snd_hda_codec_write(codec, 0x01, 0,
3765 AC_VERB_SET_GPIO_DATA, 0x06);
3768 snd_hda_codec_write(codec, 0x01, 0,
3769 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3770 snd_hda_codec_write(codec, 0x01, 0,
3771 AC_VERB_SET_GPIO_MASK, 0x1F);
3772 snd_hda_codec_write(codec, 0x01, 0,
3773 AC_VERB_SET_GPIO_DATA, 0x0C);
3785 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3787 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3802 /* Set GPIO bit 1 to 0 for rear mic */
3803 R3DI_REAR_MIC = 0,
3809 /* Set GPIO bit 2 to 0 for headphone */
3810 R3DI_HEADPHONE_OUT = 0,
3816 R3DI_DSP_DOWNLOADING = 0,
3822 static void r3di_gpio_mic_set(struct hda_codec *codec,
3828 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3838 snd_hda_codec_write(codec, codec->core.afg, 0,
3842 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3848 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3853 snd_hda_codec_write(codec, codec->core.afg, 0,
3857 /* Set DOWNLOADING bit to 0. */
3860 snd_hda_codec_write(codec, codec->core.afg, 0,
3867 snd_hda_codec_write(codec, codec->core.afg, 0,
3875 struct hda_codec *codec,
3880 struct ca0132_spec *spec = codec->spec;
3882 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3884 return 0;
3888 struct hda_codec *codec,
3891 struct ca0132_spec *spec = codec->spec;
3893 if (spec->dsp_state == DSP_DOWNLOADING)
3894 return 0;
3898 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3901 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3903 return 0;
3907 struct hda_codec *codec,
3910 struct ca0132_spec *spec = codec->spec;
3912 struct snd_pcm_runtime *runtime = substream->runtime;
3914 if (spec->dsp_state != DSP_DOWNLOADED)
3915 return 0;
3918 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3919 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3920 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3925 if (spec->cur_out_type == SPEAKER_OUT)
3928 return (latency * runtime->rate) / 1000;
3935 struct hda_codec *codec,
3938 struct ca0132_spec *spec = codec->spec;
3939 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3943 struct hda_codec *codec,
3948 struct ca0132_spec *spec = codec->spec;
3949 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3954 struct hda_codec *codec,
3957 struct ca0132_spec *spec = codec->spec;
3958 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3962 struct hda_codec *codec,
3965 struct ca0132_spec *spec = codec->spec;
3966 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3973 struct hda_codec *codec,
3978 snd_hda_codec_setup_stream(codec, hinfo->nid,
3979 stream_tag, 0, format);
3981 return 0;
3985 struct hda_codec *codec,
3988 struct ca0132_spec *spec = codec->spec;
3990 if (spec->dsp_state == DSP_DOWNLOADING)
3991 return 0;
3993 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3994 return 0;
3998 struct hda_codec *codec,
4001 struct ca0132_spec *spec = codec->spec;
4003 struct snd_pcm_runtime *runtime = substream->runtime;
4005 if (spec->dsp_state != DSP_DOWNLOADED)
4006 return 0;
4008 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4011 return (latency * runtime->rate) / 1000;
4032 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4050 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4059 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4075 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4079 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4080 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4081 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4082 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4083 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4084 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4085 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4086 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4087 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4088 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4089 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4090 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4091 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4092 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4093 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4094 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4095 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4099 * This table counts from float 0 to 1 in increments of .01, which is
4103 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4104 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4105 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4106 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4107 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4108 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4109 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4110 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4111 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4112 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4113 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4114 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4115 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4116 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4117 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4118 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4119 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4123 * This table counts from float 10 to 1000, which is the range of the x-bass
4127 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4128 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4129 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4130 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4131 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4132 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4133 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4134 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4135 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4136 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4137 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4138 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4139 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4140 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4141 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4142 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4143 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4150 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4151 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4152 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4153 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4154 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4155 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4156 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4157 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4158 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4159 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4160 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4161 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4162 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4163 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4164 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4165 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4166 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4167 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4168 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4169 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4170 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4171 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4172 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4173 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4174 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4175 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4176 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4180 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4181 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4182 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4183 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4184 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4185 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4186 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4187 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4188 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4189 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4190 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4191 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4192 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4193 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4194 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4195 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4196 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4200 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4201 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4202 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4203 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4204 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4205 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4206 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4207 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4208 0x41C00000
4211 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4216 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4218 CLASS(snd_hda_power, pm)(codec);
4219 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4226 return -EINVAL;
4232 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4233 struct ca0132_spec *spec = codec->spec;
4235 long *valp = ucontrol->value.integer.value;
4236 int idx = nid - TUNING_CTL_START_NID;
4238 *valp = spec->cur_ctl_vals[idx];
4239 return 0;
4246 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4247 uinfo->count = chs == 3 ? 2 : 1;
4248 uinfo->value.integer.min = 20;
4249 uinfo->value.integer.max = 180;
4250 uinfo->value.integer.step = 1;
4252 return 0;
4258 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4259 struct ca0132_spec *spec = codec->spec;
4261 long *valp = ucontrol->value.integer.value;
4264 idx = nid - TUNING_CTL_START_NID;
4266 if (spec->cur_ctl_vals[idx] == *valp)
4267 return 0;
4269 spec->cur_ctl_vals[idx] = *valp;
4271 idx = *valp - 20;
4272 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4282 uinfo->count = chs == 3 ? 2 : 1;
4283 uinfo->value.integer.min = 0;
4284 uinfo->value.integer.max = 100;
4285 uinfo->value.integer.step = 1;
4287 return 0;
4293 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4294 struct ca0132_spec *spec = codec->spec;
4296 long *valp = ucontrol->value.integer.value;
4299 idx = nid - TUNING_CTL_START_NID;
4301 if (spec->cur_ctl_vals[idx] == *valp)
4302 return 0;
4304 spec->cur_ctl_vals[idx] = *valp;
4307 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4309 return 0;
4316 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4317 uinfo->count = chs == 3 ? 2 : 1;
4318 uinfo->value.integer.min = 0;
4319 uinfo->value.integer.max = 48;
4320 uinfo->value.integer.step = 1;
4322 return 0;
4328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4329 struct ca0132_spec *spec = codec->spec;
4331 long *valp = ucontrol->value.integer.value;
4334 idx = nid - TUNING_CTL_START_NID;
4336 if (spec->cur_ctl_vals[idx] == *valp)
4337 return 0;
4339 spec->cur_ctl_vals[idx] = *valp;
4342 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4347 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4348 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4350 static int add_tuning_control(struct hda_codec *codec,
4357 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4382 return 0;
4385 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4387 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4390 static int add_tuning_ctls(struct hda_codec *codec)
4395 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4396 err = add_tuning_control(codec,
4401 if (err < 0)
4405 return 0;
4408 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4410 struct ca0132_spec *spec = codec->spec;
4413 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4414 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4416 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4418 /* EQ defaults to 0dB. */
4420 spec->cur_ctl_vals[i] = 24;
4427 * If jack inserted, headphone will be selected, else built-in speakers
4430 static int ca0132_select_out(struct hda_codec *codec)
4432 struct ca0132_spec *spec = codec->spec;
4439 codec_dbg(codec, "ca0132_select_out\n");
4441 CLASS(snd_hda_power_pm, pm)(codec);
4443 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4446 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4449 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4452 spec->cur_out_type = HEADPHONE_OUT;
4454 spec->cur_out_type = SPEAKER_OUT;
4456 if (spec->cur_out_type == SPEAKER_OUT) {
4457 codec_dbg(codec, "ca0132_select_out speaker\n");
4460 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4461 if (err < 0)
4465 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4466 if (err < 0)
4470 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4471 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4472 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4473 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4474 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4475 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4476 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4477 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4480 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4481 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4482 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4485 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4486 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4487 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4490 codec_dbg(codec, "ca0132_select_out hp\n");
4493 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4494 if (err < 0)
4498 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4499 if (err < 0)
4503 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4504 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4505 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4506 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4507 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4508 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4509 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4510 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4513 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4514 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4515 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4518 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4519 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4520 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4524 return 0;
4527 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4528 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4529 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4531 static void ae5_mmio_select_out(struct hda_codec *codec)
4533 struct ca0132_spec *spec = codec->spec;
4542 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4543 ca0113_mmio_command_set(codec, out_cmds->group[i],
4544 out_cmds->target[i],
4545 out_cmds->vals[spec->cur_out_type][i]);
4548 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4550 struct ca0132_spec *spec = codec->spec;
4555 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4556 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4557 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4558 return 0;
4560 /* Set front L/R full range. Zero for full-range, one for redirection. */
4561 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4562 err = dspio_set_uint_param(codec, 0x96,
4564 if (err < 0)
4567 /* When setting full-range rear, both rear and center/lfe are set. */
4568 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4569 err = dspio_set_uint_param(codec, 0x96,
4571 if (err < 0)
4574 err = dspio_set_uint_param(codec, 0x96,
4576 if (err < 0)
4580 * Only the AE series cards set this value when setting full-range,
4584 err = dspio_set_uint_param(codec, 0x96,
4586 if (err < 0)
4590 return 0;
4593 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4596 struct ca0132_spec *spec = codec->spec;
4600 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4601 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4606 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4607 if (err < 0)
4612 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4613 err = dspio_set_uint_param(codec, 0x96,
4615 if (err < 0)
4619 return 0;
4626 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4629 struct ca0132_spec *spec = codec->spec;
4634 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4642 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4646 struct ca0132_spec *spec = codec->spec;
4650 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4652 return 0;
4654 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4655 if (quirk_data->is_ae_series)
4656 ae5_mmio_select_out(codec);
4658 if (out_info->has_hda_gpio) {
4659 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4660 AC_VERB_GET_GPIO_DATA, 0);
4662 if (out_info->hda_gpio_set)
4663 gpio_data |= (1 << out_info->hda_gpio_pin);
4665 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4667 snd_hda_codec_write(codec, codec->core.afg, 0,
4671 if (out_info->mmio_gpio_count) {
4672 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4673 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4674 out_info->mmio_gpio_set[i]);
4678 if (out_info->scp_cmds_count) {
4679 for (i = 0; i < out_info->scp_cmds_count; i++) {
4680 err = dspio_set_uint_param(codec,
4681 out_info->scp_cmd_mid[i],
4682 out_info->scp_cmd_req[i],
4683 out_info->scp_cmd_val[i]);
4684 if (err < 0)
4689 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4691 if (out_info->has_chipio_write) {
4692 chipio_write(codec, out_info->chipio_write_addr,
4693 out_info->chipio_write_data);
4696 if (quirk_data->has_headphone_gain) {
4697 if (spec->cur_out_type != HEADPHONE_OUT) {
4698 if (quirk_data->is_ae_series)
4699 ae5_headphone_gain_set(codec, 2);
4701 zxr_headphone_gain_set(codec, 0);
4703 if (quirk_data->is_ae_series)
4704 ae5_headphone_gain_set(codec,
4705 spec->ae5_headphone_gain_val);
4707 zxr_headphone_gain_set(codec,
4708 spec->zxr_gain_set);
4712 return 0;
4715 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4720 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4721 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4725 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4734 * It also adds the ability to auto-detect the front headphone port.
4736 static int ca0132_alt_select_out(struct hda_codec *codec)
4738 struct ca0132_spec *spec = codec->spec;
4744 hda_nid_t headphone_nid = spec->out_pins[1];
4746 codec_dbg(codec, "%s\n", __func__);
4748 CLASS(snd_hda_power_pm, pm)(codec);
4750 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4758 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4759 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4762 spec->cur_out_type = HEADPHONE_OUT;
4764 spec->cur_out_type = SPEAKER_OUT;
4766 spec->cur_out_type = spec->out_enum_val;
4768 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4771 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4772 if (err < 0)
4775 err = ca0132_alt_select_out_quirk_set(codec);
4776 if (err < 0)
4779 switch (spec->cur_out_type) {
4781 codec_dbg(codec, "%s speaker\n", __func__);
4784 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4785 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4788 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4789 /* Set front L-R to output. */
4790 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4792 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4794 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4801 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4804 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4806 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4807 if (err < 0)
4812 codec_dbg(codec, "%s hp\n", __func__);
4813 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4814 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4817 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4818 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4819 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4822 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4823 headphone_nid = spec->out_pins[2];
4824 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4825 headphone_nid = spec->out_pins[1];
4827 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4830 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4832 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4834 if (err < 0)
4839 * If output effects are enabled, set the X-Bass effect value again to
4844 ca0132_effects_set(codec, X_BASS,
4845 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4847 /* Set speaker EQ bypass attenuation to 0. */
4848 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4849 if (err < 0)
4856 err = dspio_set_uint_param(codec, 0x96,
4858 if (err < 0)
4861 if (spec->cur_out_type == SPEAKER_OUT)
4862 err = ca0132_alt_surround_set_bass_redirection(codec,
4863 spec->bass_redirection_val);
4865 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4866 if (err < 0)
4870 err = dspio_set_uint_param(codec, 0x96,
4872 if (err < 0)
4875 if (spec->cur_out_type == SPEAKER_OUT) {
4876 err = ca0132_alt_set_full_range_speaker(codec);
4877 if (err < 0)
4881 return 0;
4891 ca0132_alt_select_out(spec->codec);
4893 ca0132_select_out(spec->codec);
4895 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4897 jack->block_report = 0;
4898 snd_hda_jack_report_sync(spec->codec);
4902 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4903 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4904 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4905 static int stop_mic1(struct hda_codec *codec);
4906 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4907 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4912 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4914 struct ca0132_spec *spec = codec->spec;
4917 if (spec->dsp_state != DSP_DOWNLOADED)
4918 return 0;
4920 /* if CrystalVoice if off, vipsource should be 0 */
4921 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4922 (val == 0)) {
4923 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4924 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4925 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4926 if (spec->cur_mic_type == DIGITAL_MIC)
4930 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4932 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4934 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4935 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4936 if (spec->cur_mic_type == DIGITAL_MIC)
4940 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4942 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4944 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4950 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4952 struct ca0132_spec *spec = codec->spec;
4955 if (spec->dsp_state != DSP_DOWNLOADED)
4956 return 0;
4958 codec_dbg(codec, "%s\n", __func__);
4960 chipio_set_stream_control(codec, 0x03, 0);
4961 chipio_set_stream_control(codec, 0x04, 0);
4963 /* if CrystalVoice is off, vipsource should be 0 */
4964 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4965 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4966 codec_dbg(codec, "%s: off.", __func__);
4967 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4970 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4972 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4973 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4975 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4978 if (spec->in_enum_val == REAR_LINE_IN)
4987 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4990 codec_dbg(codec, "%s: on.", __func__);
4991 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4992 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4994 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4996 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5000 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5003 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5006 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5009 chipio_set_stream_control(codec, 0x03, 1);
5010 chipio_set_stream_control(codec, 0x04, 1);
5018 * If jack inserted, ext.mic will be selected, else built-in mic
5021 static int ca0132_select_mic(struct hda_codec *codec)
5023 struct ca0132_spec *spec = codec->spec;
5027 codec_dbg(codec, "ca0132_select_mic\n");
5029 CLASS(snd_hda_power_pm, pm)(codec);
5031 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5034 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5037 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5040 spec->cur_mic_type = LINE_MIC_IN;
5042 spec->cur_mic_type = DIGITAL_MIC;
5044 if (spec->cur_mic_type == DIGITAL_MIC) {
5046 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5047 ca0132_set_dmic(codec, 1);
5048 ca0132_mic_boost_set(codec, 0);
5050 ca0132_effects_set(codec, VOICE_FOCUS,
5051 spec->effects_switch
5052 [VOICE_FOCUS - EFFECT_START_NID]);
5055 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5056 ca0132_set_dmic(codec, 0);
5057 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5059 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5062 return 0;
5068 * The front mic has no jack-detection, so the only way to switch to it
5071 static int ca0132_alt_select_in(struct hda_codec *codec)
5073 struct ca0132_spec *spec = codec->spec;
5076 codec_dbg(codec, "%s\n", __func__);
5078 CLASS(snd_hda_power_pm, pm)(codec);
5080 chipio_set_stream_control(codec, 0x03, 0);
5081 chipio_set_stream_control(codec, 0x04, 0);
5083 spec->cur_mic_type = spec->in_enum_val;
5085 switch (spec->cur_mic_type) {
5090 ca0113_mmio_gpio_set(codec, 0, false);
5097 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5101 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5105 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5107 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5109 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5111 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5118 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5119 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5121 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5123 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5125 chipio_set_stream_control(codec, 0x03, 1);
5126 chipio_set_stream_control(codec, 0x04, 1);
5129 chipio_write(codec, 0x18B098, 0x0000000C);
5130 chipio_write(codec, 0x18B09C, 0x0000000C);
5133 chipio_write(codec, 0x18B098, 0x0000000C);
5134 chipio_write(codec, 0x18B09C, 0x000000CC);
5137 chipio_write(codec, 0x18B098, 0x0000000C);
5138 chipio_write(codec, 0x18B09C, 0x0000004C);
5143 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5146 ca0132_mic_boost_set(codec, 0);
5150 ca0113_mmio_gpio_set(codec, 0, false);
5153 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5156 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5159 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5160 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5162 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5164 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5170 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5171 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5173 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5179 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5184 chipio_write(codec, 0x18B098, 0x00000000);
5185 chipio_write(codec, 0x18B09C, 0x00000000);
5190 chipio_set_stream_control(codec, 0x03, 1);
5191 chipio_set_stream_control(codec, 0x04, 1);
5197 ca0113_mmio_gpio_set(codec, 0, true);
5198 ca0113_mmio_gpio_set(codec, 5, false);
5202 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5206 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5214 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5215 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5217 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5219 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5221 chipio_set_stream_control(codec, 0x03, 1);
5222 chipio_set_stream_control(codec, 0x04, 1);
5226 chipio_write(codec, 0x18B098, 0x0000000C);
5227 chipio_write(codec, 0x18B09C, 0x000000CC);
5230 chipio_write(codec, 0x18B098, 0x0000000C);
5231 chipio_write(codec, 0x18B09C, 0x0000004C);
5236 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5239 ca0132_cvoice_switch_set(codec);
5241 return 0;
5247 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5251 struct ca0132_spec *spec = codec->spec;
5256 nid = spec->shared_out_nid;
5259 nid = spec->shared_mic_nid;
5273 * They return 0 if no changed. Return 1 if changed.
5275 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5277 struct ca0132_spec *spec = codec->spec;
5282 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5288 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5289 ca0132_voicefx.reqs[0], tmp);
5297 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5299 struct ca0132_spec *spec = codec->spec;
5302 int err = 0;
5303 int idx = nid - EFFECT_START_NID;
5305 if ((idx < 0) || (idx >= num_fx))
5306 return 0; /* no changed */
5311 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5312 val = 0;
5313 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5314 channel_cfg = spec->channel_cfg_val;
5317 val = 0;
5324 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5325 val = 0;
5327 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5328 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5329 val = 0;
5333 && (spec->cur_mic_type != REAR_LINE_IN)) {
5334 if (spec->effects_switch[CRYSTAL_VOICE -
5337 if (spec->effects_switch[VOICE_FOCUS -
5344 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5349 * to module ID 0x47. No clue why.
5352 && (spec->cur_mic_type != REAR_LINE_IN)) {
5353 if (spec->effects_switch[CRYSTAL_VOICE -
5355 if (spec->effects_switch[NOISE_REDUCTION -
5363 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5368 spec->in_enum_val == REAR_LINE_IN)
5369 val = 0;
5372 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5375 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5376 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5377 ca0132_effects[idx].reqs[0], on);
5379 if (err < 0)
5380 return 0; /* no changed */
5388 static int ca0132_pe_switch_set(struct hda_codec *codec)
5390 struct ca0132_spec *spec = codec->spec;
5392 int i, ret = 0;
5394 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5395 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5398 ca0132_alt_select_out(codec);
5400 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5404 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5410 static int stop_mic1(struct hda_codec *codec)
5412 struct ca0132_spec *spec = codec->spec;
5413 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5414 AC_VERB_GET_CONV, 0);
5415 if (oldval != 0)
5416 snd_hda_codec_write(codec, spec->adcs[0], 0,
5418 0);
5423 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5425 struct ca0132_spec *spec = codec->spec;
5427 if (oldval != 0)
5428 snd_hda_codec_write(codec, spec->adcs[0], 0,
5436 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5438 struct ca0132_spec *spec = codec->spec;
5440 int i, ret = 0;
5443 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5444 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5446 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5450 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5453 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5456 oldval = stop_mic1(codec);
5458 ret |= ca0132_alt_set_vipsource(codec, 1);
5460 ret |= ca0132_set_vipsource(codec, 1);
5461 resume_mic1(codec, oldval);
5465 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5467 struct ca0132_spec *spec = codec->spec;
5468 int ret = 0;
5471 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5472 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5474 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5475 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5480 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5482 struct ca0132_spec *spec = codec->spec;
5483 int ret = 0;
5485 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5486 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5490 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5494 for (i = 0; i < 4; i++)
5495 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5497 return 0;
5504 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5506 ca0113_mmio_gpio_set(codec, 1, val);
5508 return 0;
5514 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5516 hda_nid_t shared_nid = 0;
5518 int ret = 0;
5519 struct ca0132_spec *spec = codec->spec;
5524 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5527 ca0132_alt_select_out(codec);
5529 ca0132_select_out(codec);
5536 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5538 ca0132_select_mic(codec);
5544 ca0132_alt_select_out(codec);
5546 ca0132_select_out(codec);
5551 ca0132_select_mic(codec);
5556 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5562 guard(mutex)(&codec->control_mutex);
5563 pval = kcontrol->private_value;
5564 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5565 0, dir);
5567 kcontrol->private_value = pval;
5574 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5577 CLASS(snd_hda_power, pm)(codec);
5579 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5592 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5595 int i = 0;
5606 CLASS(snd_hda_power, pm)(codec);
5608 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5612 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5614 &(lookup[idx - 1]), sizeof(unsigned int));
5617 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5621 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5626 return 0;
5632 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5633 struct ca0132_spec *spec = codec->spec;
5634 long *valp = ucontrol->value.integer.value;
5638 *valp = spec->bass_redirect_xover_freq;
5640 *valp = spec->xbass_xover_freq;
5642 return 0;
5648 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5649 struct ca0132_spec *spec = codec->spec;
5651 long *valp = ucontrol->value.integer.value;
5652 int idx = nid - OUT_EFFECT_START_NID;
5654 *valp = spec->fx_ctl_val[idx];
5655 return 0;
5659 * The X-bass crossover starts at 10hz, so the min is 1. The
5665 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5666 uinfo->count = 1;
5667 uinfo->value.integer.min = 1;
5668 uinfo->value.integer.max = 100;
5669 uinfo->value.integer.step = 1;
5671 return 0;
5679 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5680 uinfo->count = chs == 3 ? 2 : 1;
5681 uinfo->value.integer.min = 0;
5682 uinfo->value.integer.max = 100;
5683 uinfo->value.integer.step = 1;
5685 return 0;
5691 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5692 struct ca0132_spec *spec = codec->spec;
5694 long *valp = ucontrol->value.integer.value;
5699 cur_val = &spec->bass_redirect_xover_freq;
5701 cur_val = &spec->xbass_xover_freq;
5705 return 0;
5711 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5713 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5715 return 0;
5721 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5722 struct ca0132_spec *spec = codec->spec;
5724 long *valp = ucontrol->value.integer.value;
5727 idx = nid - EFFECT_START_NID;
5729 if (spec->fx_ctl_val[idx] == *valp)
5730 return 0;
5732 spec->fx_ctl_val[idx] = *valp;
5735 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5737 return 0;
5744 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5755 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5756 uinfo->count = 1;
5757 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5758 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5759 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5760 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5761 strscpy(uinfo->value.enumerated.name, namestr);
5762 return 0;
5768 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5769 struct ca0132_spec *spec = codec->spec;
5771 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5772 return 0;
5778 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5779 struct ca0132_spec *spec = codec->spec;
5780 int sel = ucontrol->value.enumerated.item[0];
5784 return 0;
5786 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5789 spec->mic_boost_enum_val = sel;
5791 if (spec->in_enum_val != REAR_LINE_IN)
5792 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5798 * Sound BlasterX AE-5 Headphone Gain Controls.
5807 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5808 uinfo->count = 1;
5809 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5810 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5811 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5813 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5815 strscpy(uinfo->value.enumerated.name, namestr);
5816 return 0;
5822 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5823 struct ca0132_spec *spec = codec->spec;
5825 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5826 return 0;
5832 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5833 struct ca0132_spec *spec = codec->spec;
5834 int sel = ucontrol->value.enumerated.item[0];
5838 return 0;
5840 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5843 spec->ae5_headphone_gain_val = sel;
5845 if (spec->out_enum_val == HEADPHONE_OUT)
5846 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5852 * Sound BlasterX AE-5 sound filter enumerated control.
5861 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5862 uinfo->count = 1;
5863 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5864 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5865 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5867 ae5_filter_presets[uinfo->value.enumerated.item].name);
5868 strscpy(uinfo->value.enumerated.name, namestr);
5869 return 0;
5875 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5876 struct ca0132_spec *spec = codec->spec;
5878 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5879 return 0;
5885 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5886 struct ca0132_spec *spec = codec->spec;
5887 int sel = ucontrol->value.enumerated.item[0];
5891 return 0;
5893 codec_dbg(codec, "ae5_sound_filter: %s\n",
5896 spec->ae5_filter_val = sel;
5898 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5906 * front microphone has no auto-detect, and we need a way to set the rear
5907 * as line-in
5912 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5913 uinfo->count = 1;
5914 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5915 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5916 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5917 strscpy(uinfo->value.enumerated.name,
5918 in_src_str[uinfo->value.enumerated.item]);
5919 return 0;
5925 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5926 struct ca0132_spec *spec = codec->spec;
5928 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5929 return 0;
5935 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5936 struct ca0132_spec *spec = codec->spec;
5937 int sel = ucontrol->value.enumerated.item[0];
5941 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5942 * line-in.
5948 return 0;
5950 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5953 spec->in_enum_val = sel;
5955 ca0132_alt_select_in(codec);
5964 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5965 uinfo->count = 1;
5966 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5967 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5968 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5969 strscpy(uinfo->value.enumerated.name,
5970 out_type_str[uinfo->value.enumerated.item]);
5971 return 0;
5977 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5978 struct ca0132_spec *spec = codec->spec;
5980 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5981 return 0;
5987 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5988 struct ca0132_spec *spec = codec->spec;
5989 int sel = ucontrol->value.enumerated.item[0];
5994 return 0;
5996 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5999 spec->out_enum_val = sel;
6001 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6004 ca0132_alt_select_out(codec);
6015 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6016 uinfo->count = 1;
6017 uinfo->value.enumerated.items = items;
6018 if (uinfo->value.enumerated.item >= items)
6019 uinfo->value.enumerated.item = items - 1;
6020 strscpy(uinfo->value.enumerated.name,
6021 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6022 return 0;
6028 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6029 struct ca0132_spec *spec = codec->spec;
6031 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6032 return 0;
6038 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6039 struct ca0132_spec *spec = codec->spec;
6040 int sel = ucontrol->value.enumerated.item[0];
6044 return 0;
6046 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6049 spec->channel_cfg_val = sel;
6051 if (spec->out_enum_val == SPEAKER_OUT)
6052 ca0132_alt_select_out(codec);
6068 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6069 uinfo->count = 1;
6070 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6071 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6072 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6073 strscpy(uinfo->value.enumerated.name,
6074 out_svm_set_enum_str[uinfo->value.enumerated.item]);
6075 return 0;
6081 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6082 struct ca0132_spec *spec = codec->spec;
6084 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6085 return 0;
6091 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6092 struct ca0132_spec *spec = codec->spec;
6093 int sel = ucontrol->value.enumerated.item[0];
6095 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6099 return 0;
6101 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6104 spec->smart_volume_setting = sel;
6107 case 0:
6121 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6132 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6133 uinfo->count = 1;
6134 uinfo->value.enumerated.items = items;
6135 if (uinfo->value.enumerated.item >= items)
6136 uinfo->value.enumerated.item = items - 1;
6137 strscpy(uinfo->value.enumerated.name,
6138 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6139 return 0;
6145 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6146 struct ca0132_spec *spec = codec->spec;
6148 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6149 return 0;
6155 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6156 struct ca0132_spec *spec = codec->spec;
6157 int i, err = 0;
6158 int sel = ucontrol->value.enumerated.item[0];
6162 return 0;
6164 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6167 * Idx 0 is default.
6170 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6171 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6174 if (err < 0)
6178 if (err >= 0)
6179 spec->eq_preset_val = sel;
6189 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6190 uinfo->count = 1;
6191 uinfo->value.enumerated.items = items;
6192 if (uinfo->value.enumerated.item >= items)
6193 uinfo->value.enumerated.item = items - 1;
6194 strscpy(uinfo->value.enumerated.name,
6195 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6196 return 0;
6202 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6203 struct ca0132_spec *spec = codec->spec;
6205 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6206 return 0;
6212 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6213 struct ca0132_spec *spec = codec->spec;
6214 int i, err = 0;
6215 int sel = ucontrol->value.enumerated.item[0];
6218 return 0;
6220 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6224 * Idx 0 is default.
6227 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6228 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6231 if (err < 0)
6235 if (err >= 0) {
6236 spec->voicefx_val = sel;
6238 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6247 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6248 struct ca0132_spec *spec = codec->spec;
6251 long *valp = ucontrol->value.integer.value;
6256 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6260 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6263 return 0;
6268 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6269 return 0;
6273 if (nid == spec->input_pins[0]) {
6274 *valp = spec->cur_mic_boost;
6275 return 0;
6279 *valp = spec->zxr_gain_set;
6280 return 0;
6284 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6285 return 0;
6289 *valp = spec->bass_redirection_val;
6290 return 0;
6293 return 0;
6299 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6300 struct ca0132_spec *spec = codec->spec;
6303 long *valp = ucontrol->value.integer.value;
6305 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6308 CLASS(snd_hda_power, pm)(codec);
6312 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6316 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6324 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6325 return ca0132_pe_switch_set(codec);
6330 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6331 return ca0132_cvoice_switch_set(codec);
6337 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6338 return ca0132_effects_set(codec, nid, *valp);
6342 if (nid == spec->input_pins[0]) {
6343 spec->cur_mic_boost = *valp;
6345 if (spec->in_enum_val != REAR_LINE_IN)
6346 return ca0132_mic_boost_set(codec, *valp);
6349 if (spec->cur_mic_type != DIGITAL_MIC)
6350 return ca0132_mic_boost_set(codec, *valp);
6357 spec->zxr_gain_set = *valp;
6358 if (spec->cur_out_type == HEADPHONE_OUT)
6359 return zxr_headphone_gain_set(codec, *valp);
6361 return 0;
6365 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6366 if (spec->cur_out_type == SPEAKER_OUT)
6367 ca0132_alt_set_full_range_speaker(codec);
6369 return 0;
6373 spec->bass_redirection_val = *valp;
6374 if (spec->cur_out_type == SPEAKER_OUT)
6375 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6377 return 0;
6391 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6393 struct ca0132_spec *spec = codec->spec;
6402 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6404 dspio_set_uint_param(codec,
6406 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6409 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6411 dspio_set_uint_param(codec,
6416 dspio_set_uint_param(codec,
6424 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6425 struct ca0132_spec *spec = codec->spec;
6435 nid = spec->shared_out_nid;
6436 scoped_guard(mutex, &codec->control_mutex) {
6437 pval = kcontrol->private_value;
6438 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6440 kcontrol->private_value = pval;
6445 nid = spec->shared_mic_nid;
6446 scoped_guard(mutex, &codec->control_mutex) {
6447 pval = kcontrol->private_value;
6448 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6450 kcontrol->private_value = pval;
6462 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6463 struct ca0132_spec *spec = codec->spec;
6466 long *valp = ucontrol->value.integer.value;
6470 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6474 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6477 return 0;
6483 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6484 struct ca0132_spec *spec = codec->spec;
6487 long *valp = ucontrol->value.integer.value;
6488 hda_nid_t shared_nid = 0;
6494 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6498 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6503 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6508 CLASS(snd_hda_power, pm)(codec);
6509 guard(mutex)(&codec->control_mutex);
6510 pval = kcontrol->private_value;
6511 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6512 0, dir);
6514 kcontrol->private_value = pval;
6528 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6529 struct ca0132_spec *spec = codec->spec;
6532 long *valp = ucontrol->value.integer.value;
6533 hda_nid_t vnid = 0;
6536 case 0x02:
6539 case 0x07:
6546 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6550 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6554 CLASS(snd_hda_power, pm)(codec);
6555 ca0132_alt_dsp_volume_put(codec, vnid);
6556 guard(mutex)(&codec->control_mutex);
6563 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6564 struct ca0132_spec *spec = codec->spec;
6574 nid = spec->shared_out_nid;
6575 scoped_guard(mutex, &codec->control_mutex) {
6576 pval = kcontrol->private_value;
6577 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6579 kcontrol->private_value = pval;
6584 nid = spec->shared_mic_nid;
6585 scoped_guard(mutex, &codec->control_mutex) {
6586 pval = kcontrol->private_value;
6587 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6589 kcontrol->private_value = pval;
6599 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6605 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6622 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6626 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6634 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6637 struct ca0132_spec *spec = codec->spec;
6650 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6653 static int add_voicefx(struct hda_codec *codec)
6657 VOICEFX, 1, 0, HDA_INPUT);
6661 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6665 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6669 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6673 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6674 snd_ctl_new1(&knew, codec));
6682 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6686 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6690 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6691 snd_ctl_new1(&knew, codec));
6699 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6703 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6707 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6708 snd_ctl_new1(&knew, codec));
6716 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6720 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6724 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6725 snd_ctl_new1(&knew, codec));
6733 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6736 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6739 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6740 snd_ctl_new1(&knew, codec));
6743 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6746 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6749 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6750 snd_ctl_new1(&knew, codec));
6755 * channel on speakers that are set as not being full-range. On configurations
6757 * replacement for X-Bass on configurations with an LFE channel.
6759 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6763 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6771 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6772 snd_ctl_new1(&knew, codec));
6775 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6782 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6783 snd_ctl_new1(&knew, codec));
6788 * because the front microphone has no auto-detect, and Line-in has to be set
6791 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6795 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6799 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6800 snd_ctl_new1(&knew, codec));
6804 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6807 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6811 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6815 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6816 snd_ctl_new1(&knew, codec));
6821 * Add headphone gain enumerated control for the AE-5. This switches between
6822 * three modes, low, medium, and high. When non-headphone outputs are selected,
6825 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6828 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6829 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6833 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6834 snd_ctl_new1(&knew, codec));
6838 * Add sound filter enumerated control for the AE-5. This adds three different
6842 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6845 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6846 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6850 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6851 snd_ctl_new1(&knew, codec));
6854 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6860 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6861 snd_ctl_new1(&knew, codec));
6874 * I think this has to do with the pin for rear surround being 0x11,
6875 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6891 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6893 int err = 0;
6896 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6898 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6903 if (hinfo->channels_max == 6) {
6904 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6906 elem, hinfo->channels_max, 0, &chmap);
6907 if (err < 0)
6908 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6922 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6923 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6924 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6925 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6926 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6927 0x12, 1, HDA_INPUT),
6940 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6945 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6947 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6948 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6949 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6950 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6951 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6952 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6953 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6955 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6956 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6967 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6969 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6970 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6971 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6972 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6973 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6974 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6977 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6978 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6984 static int ca0132_build_controls(struct hda_codec *codec)
6986 struct ca0132_spec *spec = codec->spec;
6988 int err = 0;
6991 for (i = 0; i < spec->num_mixers; i++) {
6992 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6993 if (err < 0)
6998 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6999 spec->tlv);
7000 snd_hda_add_vmaster(codec, "Master Playback Volume",
7001 spec->tlv, ca0132_alt_follower_pfxs,
7002 "Playback Volume", 0);
7003 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7006 true, 0, &spec->vmaster_mute.sw_kctl);
7007 if (err < 0)
7015 for (i = 0; i < num_fx; i++) {
7018 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7023 err = add_fx_switch(codec, ca0132_effects[i].nid,
7026 if (err < 0)
7030 * If codec has use_alt_controls set to true, add effect level sliders,
7035 err = ca0132_alt_add_svm_enum(codec);
7036 if (err < 0)
7039 err = add_ca0132_alt_eq_presets(codec);
7040 if (err < 0)
7043 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7044 "Enable OutFX", 0);
7045 if (err < 0)
7048 err = add_fx_switch(codec, CRYSTAL_VOICE,
7050 if (err < 0)
7053 num_sliders = OUT_EFFECTS_COUNT - 1;
7054 for (i = 0; i < num_sliders; i++) {
7055 err = ca0132_alt_add_effect_slider(codec,
7059 if (err < 0)
7063 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7064 "X-Bass Crossover", EFX_DIR_OUT);
7066 if (err < 0)
7069 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7070 "PlayEnhancement", 0);
7071 if (err < 0)
7074 err = add_fx_switch(codec, CRYSTAL_VOICE,
7076 if (err < 0)
7079 err = add_voicefx(codec);
7080 if (err < 0)
7084 * If the codec uses alt_functions, you need the enumerated controls
7089 err = ca0132_alt_add_output_enum(codec);
7090 if (err < 0)
7092 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7093 if (err < 0)
7095 err = ca0132_alt_add_front_full_range_switch(codec);
7096 if (err < 0)
7098 err = ca0132_alt_add_rear_full_range_switch(codec);
7099 if (err < 0)
7101 err = ca0132_alt_add_bass_redirection_crossover(codec);
7102 if (err < 0)
7104 err = ca0132_alt_add_bass_redirection_switch(codec);
7105 if (err < 0)
7107 err = ca0132_alt_add_mic_boost_enum(codec);
7108 if (err < 0)
7112 * header on the card, and aux-in is handled by the DBPro board.
7115 err = ca0132_alt_add_input_enum(codec);
7116 if (err < 0)
7124 err = ae5_add_headphone_gain_enum(codec);
7125 if (err < 0)
7127 err = ae5_add_sound_filter_enum(codec);
7128 if (err < 0)
7132 err = zxr_add_headphone_gain_switch(codec);
7133 if (err < 0)
7141 add_tuning_ctls(codec);
7144 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7145 if (err < 0)
7148 if (spec->dig_out) {
7149 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7150 spec->dig_out);
7151 if (err < 0)
7153 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7154 if (err < 0)
7156 /* spec->multiout.share_spdif = 1; */
7159 if (spec->dig_in) {
7160 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7161 if (err < 0)
7166 ca0132_alt_add_chmap_ctls(codec);
7168 return 0;
7171 static int dbpro_build_controls(struct hda_codec *codec)
7173 struct ca0132_spec *spec = codec->spec;
7174 int err = 0;
7176 if (spec->dig_out) {
7177 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7178 spec->dig_out);
7179 if (err < 0)
7183 if (spec->dig_in) {
7184 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7185 if (err < 0)
7189 return 0;
7235 static int ca0132_build_pcms(struct hda_codec *codec)
7237 struct ca0132_spec *spec = codec->spec;
7240 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7242 return -ENOMEM;
7244 info->own_chmap = true;
7245 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7248 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7249 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7250 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7251 spec->multiout.max_channels;
7252 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7253 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7254 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7258 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7260 return -ENOMEM;
7261 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7263 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7264 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7267 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7269 return -ENOMEM;
7270 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7271 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7272 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7274 if (!spec->dig_out && !spec->dig_in)
7275 return 0;
7277 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7279 return -ENOMEM;
7280 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7281 if (spec->dig_out) {
7282 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7284 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7286 if (spec->dig_in) {
7287 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7289 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7292 return 0;
7295 static int dbpro_build_pcms(struct hda_codec *codec)
7297 struct ca0132_spec *spec = codec->spec;
7300 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7302 return -ENOMEM;
7303 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7304 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7308 if (!spec->dig_out && !spec->dig_in)
7309 return 0;
7311 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7313 return -ENOMEM;
7314 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7315 if (spec->dig_out) {
7316 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7318 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7320 if (spec->dig_in) {
7321 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7323 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7326 return 0;
7329 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7332 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7333 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7334 snd_hda_codec_write(codec, pin, 0,
7338 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7339 snd_hda_codec_write(codec, dac, 0,
7343 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7346 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7347 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7348 snd_hda_codec_write(codec, pin, 0,
7350 AMP_IN_UNMUTE(0));
7352 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7353 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7354 AMP_IN_UNMUTE(0));
7356 /* init to 0 dB and unmute. */
7357 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7358 HDA_AMP_VOLMASK, 0x5a);
7359 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7360 HDA_AMP_MUTE, 0);
7364 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7368 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7370 snd_hda_override_amp_caps(codec, nid, dir, caps);
7374 * Switch between Digital built-in mic and analog mic.
7376 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7378 struct ca0132_spec *spec = codec->spec;
7383 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7385 oldval = stop_mic1(codec);
7386 ca0132_set_vipsource(codec, 0);
7388 /* set DMic input as 2-ch */
7390 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7392 val = spec->dmic_ctl;
7393 val |= 0x80;
7394 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7397 if (!(spec->dmic_ctl & 0x20))
7398 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7402 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7404 val = spec->dmic_ctl;
7406 val &= 0x5f;
7407 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7410 if (!(spec->dmic_ctl & 0x20))
7411 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7413 ca0132_set_vipsource(codec, 1);
7414 resume_mic1(codec, oldval);
7420 static void ca0132_init_dmic(struct hda_codec *codec)
7422 struct ca0132_spec *spec = codec->spec;
7430 * Bit 2-0: MPIO select
7432 * Bit 7-4: reserved
7434 val = 0x01;
7435 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7439 * Bit 2-0: Data1 MPIO select
7441 * Bit 6-4: Data2 MPIO select
7444 val = 0x83;
7445 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7448 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7449 * Bit 3-0: Channel mask
7456 val = 0x33;
7458 val = 0x23;
7460 spec->dmic_ctl = val;
7461 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7468 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7470 struct ca0132_spec *spec = codec->spec;
7472 guard(mutex)(&spec->chipio_mutex);
7474 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7475 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7478 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7480 struct ca0132_spec *spec = codec->spec;
7483 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7484 snd_hda_codec_update_widgets(codec);
7486 for (i = 0; i < spec->multiout.num_dacs; i++)
7487 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7489 for (i = 0; i < spec->num_outputs; i++)
7490 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7492 for (i = 0; i < spec->num_inputs; i++) {
7493 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7494 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7500 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7506 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7507 if (status >= 0) {
7508 /* AND against 0xfff to get the active channel bits. */
7509 tmp = tmp & 0xfff;
7515 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7524 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7525 if (dsp_is_dma_active(codec, i)) {
7526 status = dspio_free_dma_chan(codec, i);
7527 if (status < 0)
7528 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7539 * cause of most of the no-audio on startup issues were due to improperly
7552 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7553 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7555 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7557 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7558 struct ca0132_spec *spec = codec->spec;
7565 scoped_guard(mutex, &spec->chipio_mutex) {
7566 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7567 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7570 chipio_set_stream_control(codec,
7571 dsp_dma_stream_ids[i], 0);
7581 ca0132_alt_free_active_dma_channels(codec);
7583 guard(mutex)(&spec->chipio_mutex);
7585 /* Make sure stream 0x0c is six channels. */
7586 chipio_set_stream_channels(codec, 0x0c, 6);
7588 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7589 chipio_set_stream_control(codec,
7598 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7600 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7601 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7604 * 0x0001f8c0
7608 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7609 * entry within the 0x190000 range, and when a range of entries is in use, the
7610 * ending value is overwritten with 0xff.
7611 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7612 * streamID's, where each entry is a starting 0x190000 port offset.
7613 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7621 * 0x00-0x1f: HDA audio stream input/output ports.
7622 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7623 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7624 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7625 * 0xe0-0xff: DAC/ADC audio input/output ports.
7628 * 0x03: Mic1 ADC to DSP.
7629 * 0x04: Mic2 ADC to DSP.
7630 * 0x05: HDA node 0x02 audio stream to DSP.
7631 * 0x0f: DSP Mic exit to HDA node 0x07.
7632 * 0x0c: DSP processed audio to DACs.
7633 * 0x14: DAC0, front L/R.
7641 static void chipio_remap_stream(struct hda_codec *codec,
7647 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7651 * Check if the stream's port value is 0xff, because the 8051 may not
7655 if (stream_offset == 0xff) {
7656 for (i = 0; i < 5; i++) {
7659 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7662 if (stream_offset != 0xff)
7667 if (stream_offset == 0xff) {
7668 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7669 __func__, remap_data->stream_id);
7673 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7674 stream_offset *= 0x04;
7675 stream_offset += 0x190000;
7677 for (i = 0; i < remap_data->count; i++) {
7678 chipio_write_no_mutex(codec,
7679 stream_offset + remap_data->offset[i],
7680 remap_data->value[i]);
7684 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7691 /* Non-zero values are floating point 0.000198. */
7692 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7696 /* Non-zero values are floating point 0.000220. */
7697 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7701 /* Non-zero values are floating point 0.000100. */
7702 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7708 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7710 struct ca0132_spec *spec = codec->spec;
7731 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7736 dspio_set_uint_param(codec, 0x96, i, tmp);
7741 dspio_set_uint_param(codec, 0x96, i, tmp);
7744 for (i = 0; i < 6; i++)
7745 dspio_set_uint_param(codec, 0x96,
7750 * Initialize mic for non-chromebook ca0132 implementations.
7752 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7754 struct ca0132_spec *spec = codec->spec;
7758 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7759 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7761 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7765 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7768 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7769 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7771 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7773 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7777 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7778 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7782 static void sbz_connect_streams(struct hda_codec *codec)
7784 struct ca0132_spec *spec = codec->spec;
7786 guard(mutex)(&spec->chipio_mutex);
7788 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7790 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7791 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7793 /* Setup stream 0x14 with it's source and destination points */
7794 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7795 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7796 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7797 chipio_set_stream_channels(codec, 0x14, 2);
7798 chipio_set_stream_control(codec, 0x14, 1);
7800 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7809 static void sbz_chipio_startup_data(struct hda_codec *codec)
7812 struct ca0132_spec *spec = codec->spec;
7814 guard(mutex)(&spec->chipio_mutex);
7815 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7818 chipio_remap_stream(codec, &stream_remap_data[0]);
7836 chipio_remap_stream(codec, dsp_out_remap_data);
7838 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7841 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7843 struct ca0132_spec *spec = codec->spec;
7846 chipio_set_stream_control(codec, 0x03, 0);
7847 chipio_set_stream_control(codec, 0x04, 0);
7849 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7850 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7853 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7855 chipio_set_stream_control(codec, 0x03, 1);
7856 chipio_set_stream_control(codec, 0x04, 1);
7860 chipio_write(codec, 0x18b098, 0x0000000c);
7861 chipio_write(codec, 0x18b09C, 0x0000000c);
7864 chipio_write(codec, 0x18b098, 0x0000000c);
7865 chipio_write(codec, 0x18b09c, 0x0000004c);
7872 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7874 struct ca0132_spec *spec = codec->spec;
7876 chipio_8051_write_direct(codec, 0x93, 0x10);
7877 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7879 writeb(0xff, spec->mem_base + 0x304);
7880 writeb(0xff, spec->mem_base + 0x304);
7881 writeb(0xff, spec->mem_base + 0x304);
7882 writeb(0xff, spec->mem_base + 0x304);
7883 writeb(0x00, spec->mem_base + 0x100);
7884 writeb(0xff, spec->mem_base + 0x304);
7885 writeb(0x00, spec->mem_base + 0x100);
7886 writeb(0xff, spec->mem_base + 0x304);
7887 writeb(0x00, spec->mem_base + 0x100);
7888 writeb(0xff, spec->mem_base + 0x304);
7889 writeb(0x00, spec->mem_base + 0x100);
7890 writeb(0xff, spec->mem_base + 0x304);
7892 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7893 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7894 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7897 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7902 * AE-5's registry values in Windows.
7904 chipio_set_control_param(codec, 3, 0);
7907 * change colors on the external LED strip connected to the AE-5.
7909 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7912 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7914 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7917 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7919 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7920 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7921 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7922 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7923 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7926 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7928 struct ca0132_spec *spec = codec->spec;
7930 guard(mutex)(&spec->chipio_mutex);
7932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7934 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7936 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7938 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7939 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7940 chipio_set_stream_channels(codec, 0x18, 6);
7941 chipio_set_stream_control(codec, 0x18, 1);
7943 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7945 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7947 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7950 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7952 struct ca0132_spec *spec = codec->spec;
7954 guard(mutex)(&spec->chipio_mutex);
7956 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7957 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7958 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7959 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7961 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7962 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7963 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7964 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7965 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7966 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7967 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7968 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7969 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7970 ca0113_mmio_gpio_set(codec, 0, true);
7971 ca0113_mmio_gpio_set(codec, 1, true);
7972 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7974 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7976 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7977 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7980 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7982 struct ca0132_spec *spec = codec->spec;
7984 guard(mutex)(&spec->chipio_mutex);
7987 chipio_remap_stream(codec, &stream_remap_data[1]);
7989 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7990 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7991 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7992 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7993 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7994 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7995 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7996 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7999 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8001 struct ca0132_spec *spec = codec->spec;
8003 guard(mutex)(&spec->chipio_mutex);
8005 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8006 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8008 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8010 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8011 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8013 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8014 chipio_set_stream_channels(codec, 0x18, 6);
8015 chipio_set_stream_control(codec, 0x18, 1);
8017 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8020 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8023 0x41, 0x45, 0x40, 0x43, 0x51
8026 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8030 for (i = 0; i < ARRAY_SIZE(addr); i++)
8031 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8034 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8036 struct ca0132_spec *spec = codec->spec;
8038 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8041 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8045 guard(mutex)(&spec->chipio_mutex);
8047 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8049 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8050 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8051 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8052 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8054 ae7_post_dsp_pll_setup(codec);
8055 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8057 for (i = 0; i < ARRAY_SIZE(target); i++)
8058 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8060 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8061 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8062 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8064 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8065 chipio_set_stream_channels(codec, 0x21, 2);
8066 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8068 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8074 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8076 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8080 * seemingly sends data to the HDA node 0x09, which is the digital
8082 * know what data is being sent. Interestingly, the AE-5 seems to go
8084 * step, but the AE-7 does.
8087 ca0113_mmio_gpio_set(codec, 0, 1);
8088 ca0113_mmio_gpio_set(codec, 1, 1);
8090 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8091 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8092 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8093 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8095 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8096 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8098 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8099 chipio_set_stream_channels(codec, 0x18, 6);
8105 ae7_post_dsp_pll_setup(codec);
8106 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8114 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8116 chipio_8051_write_direct(codec, 0x93, 0x10);
8118 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8120 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8121 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8123 chipio_set_control_param(codec, 3, 3);
8124 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8127 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8128 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8130 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8132 ae7_post_dsp_pll_setup(codec);
8133 ae7_post_dsp_asi_stream_setup(codec);
8135 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8137 ae7_post_dsp_asi_setup_ports(codec);
8143 static void ca0132_setup_defaults(struct hda_codec *codec)
8145 struct ca0132_spec *spec = codec->spec;
8150 if (spec->dsp_state != DSP_DOWNLOADED)
8155 for (idx = 0; idx < num_fx; idx++) {
8156 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8157 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8165 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8168 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8172 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8173 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8177 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8181 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8188 static void r3d_setup_defaults(struct hda_codec *codec)
8190 struct ca0132_spec *spec = codec->spec;
8195 if (spec->dsp_state != DSP_DOWNLOADED)
8198 ca0132_alt_init_analog_mics(codec);
8199 ca0132_alt_start_dsp_audio_streams(codec);
8203 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8207 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8208 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8211 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8214 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8218 ca0113_mmio_gpio_set(codec, 2, false);
8219 ca0113_mmio_gpio_set(codec, 4, true);
8224 for (idx = 0; idx < num_fx; idx++) {
8225 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8226 dspio_set_uint_param(codec,
8238 static void sbz_setup_defaults(struct hda_codec *codec)
8240 struct ca0132_spec *spec = codec->spec;
8245 if (spec->dsp_state != DSP_DOWNLOADED)
8248 ca0132_alt_init_analog_mics(codec);
8249 ca0132_alt_start_dsp_audio_streams(codec);
8250 sbz_connect_streams(codec);
8251 sbz_chipio_startup_data(codec);
8258 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8259 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8263 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8267 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8268 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8271 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8273 ca0132_alt_dsp_initial_mic_setup(codec);
8277 for (idx = 0; idx < num_fx; idx++) {
8278 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8279 dspio_set_uint_param(codec,
8286 ca0132_alt_init_speaker_tuning(codec);
8290 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8292 static void ae5_setup_defaults(struct hda_codec *codec)
8294 struct ca0132_spec *spec = codec->spec;
8299 if (spec->dsp_state != DSP_DOWNLOADED)
8302 ca0132_alt_init_analog_mics(codec);
8303 ca0132_alt_start_dsp_audio_streams(codec);
8307 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8308 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8309 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8310 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8312 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8313 ca0113_mmio_gpio_set(codec, 0, false);
8314 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8318 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8319 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8323 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8327 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8328 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8331 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8333 ca0132_alt_dsp_initial_mic_setup(codec);
8334 ae5_post_dsp_register_set(codec);
8335 ae5_post_dsp_param_setup(codec);
8336 ae5_post_dsp_pll_setup(codec);
8337 ae5_post_dsp_stream_setup(codec);
8338 ae5_post_dsp_startup_data(codec);
8342 for (idx = 0; idx < num_fx; idx++) {
8343 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8344 dspio_set_uint_param(codec,
8351 ca0132_alt_init_speaker_tuning(codec);
8355 * Setup default parameters for the Sound Blaster AE-7 DSP.
8357 static void ae7_setup_defaults(struct hda_codec *codec)
8359 struct ca0132_spec *spec = codec->spec;
8364 if (spec->dsp_state != DSP_DOWNLOADED)
8367 ca0132_alt_init_analog_mics(codec);
8368 ca0132_alt_start_dsp_audio_streams(codec);
8369 ae7_post_dsp_setup_ports(codec);
8372 dspio_set_uint_param(codec, 0x96,
8374 dspio_set_uint_param(codec, 0x96,
8377 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8380 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8381 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8383 ca0113_mmio_gpio_set(codec, 0, false);
8387 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8388 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8392 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8396 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8397 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8400 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8401 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8407 ca0132_alt_init_analog_mics(codec);
8409 ae7_post_dsp_asi_setup(codec);
8412 * Not sure why, but these are both set to 1. They're only set to 0
8415 ca0113_mmio_gpio_set(codec, 0, true);
8416 ca0113_mmio_gpio_set(codec, 1, true);
8419 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8420 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8421 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8425 for (idx = 0; idx < num_fx; idx++) {
8426 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8427 dspio_set_uint_param(codec,
8434 ca0132_alt_init_speaker_tuning(codec);
8440 static void ca0132_init_flags(struct hda_codec *codec)
8442 struct ca0132_spec *spec = codec->spec;
8445 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8446 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8447 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8448 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8449 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8450 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8451 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8452 chipio_set_control_flag(codec,
8453 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8454 chipio_set_control_flag(codec,
8457 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8458 chipio_set_control_flag(codec,
8459 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8460 chipio_set_control_flag(codec,
8461 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8462 chipio_set_control_flag(codec,
8463 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8464 chipio_set_control_flag(codec,
8465 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8466 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8473 static void ca0132_init_params(struct hda_codec *codec)
8475 struct ca0132_spec *spec = codec->spec;
8478 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8479 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8480 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8481 chipio_set_control_param(codec, 0, 0);
8482 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8485 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8486 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8489 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8491 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8492 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8493 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8494 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8495 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8496 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8498 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8499 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8500 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8503 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8506 struct ca0132_spec *spec = codec->spec;
8519 codec->card->dev) != 0)
8520 codec_dbg(codec, "Desktop firmware not found.");
8522 codec_dbg(codec, "Desktop firmware selected.");
8526 codec->card->dev) != 0)
8527 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8529 codec_dbg(codec, "Recon3Di firmware selected.");
8536 * exists for your particular codec.
8539 codec_dbg(codec, "Default firmware selected.");
8541 codec->card->dev) != 0)
8545 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8546 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8547 codec_err(codec, "ca0132 DSP load image failed\n");
8551 dsp_loaded = dspload_wait_loaded(codec);
8559 static void ca0132_download_dsp(struct hda_codec *codec)
8561 struct ca0132_spec *spec = codec->spec;
8567 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8570 chipio_enable_clocks(codec);
8571 if (spec->dsp_state != DSP_DOWNLOADED) {
8572 spec->dsp_state = DSP_DOWNLOADING;
8574 if (!ca0132_download_dsp_images(codec))
8575 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8577 spec->dsp_state = DSP_DOWNLOADED;
8581 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8582 ca0132_set_dsp_msr(codec, true);
8585 static void ca0132_process_dsp_response(struct hda_codec *codec,
8588 struct ca0132_spec *spec = codec->spec;
8590 codec_dbg(codec, "ca0132_process_dsp_response\n");
8591 CLASS(snd_hda_power_pm, pm)(codec);
8592 if (spec->wait_scp) {
8593 if (dspio_get_response_data(codec) >= 0)
8594 spec->wait_scp = 0;
8597 dspio_clear_response_queue(codec);
8600 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8602 struct ca0132_spec *spec = codec->spec;
8605 /* Delay enabling the HP amp, to let the mic-detection
8608 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8610 tbl->block_report = 1;
8611 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8614 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8616 struct ca0132_spec *spec = codec->spec;
8619 ca0132_alt_select_in(codec);
8621 ca0132_select_mic(codec);
8624 static void ca0132_setup_unsol(struct hda_codec *codec)
8626 struct ca0132_spec *spec = codec->spec;
8627 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8628 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8630 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8634 snd_hda_jack_detect_enable_callback(codec,
8635 spec->unsol_tag_front_hp, hp_callback);
8645 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8652 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8654 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8662 {0x15, 0x70D, 0xF0},
8663 {0x15, 0x70E, 0xFE},
8664 {0x15, 0x707, 0x75},
8665 {0x15, 0x707, 0xD3},
8666 {0x15, 0x707, 0x09},
8667 {0x15, 0x707, 0x53},
8668 {0x15, 0x707, 0xD4},
8669 {0x15, 0x707, 0xEF},
8670 {0x15, 0x707, 0x75},
8671 {0x15, 0x707, 0xD3},
8672 {0x15, 0x707, 0x09},
8673 {0x15, 0x707, 0x02},
8674 {0x15, 0x707, 0x37},
8675 {0x15, 0x707, 0x78},
8676 {0x15, 0x53C, 0xCE},
8677 {0x15, 0x575, 0xC9},
8678 {0x15, 0x53D, 0xCE},
8679 {0x15, 0x5B7, 0xC9},
8680 {0x15, 0x70D, 0xE8},
8681 {0x15, 0x70E, 0xFE},
8682 {0x15, 0x707, 0x02},
8683 {0x15, 0x707, 0x68},
8684 {0x15, 0x707, 0x62},
8685 {0x15, 0x53A, 0xCE},
8686 {0x15, 0x546, 0xC9},
8687 {0x15, 0x53B, 0xCE},
8688 {0x15, 0x5E8, 0xC9},
8694 {0x15, 0x70D, 0x20},
8695 {0x15, 0x70E, 0x19},
8696 {0x15, 0x707, 0x00},
8697 {0x15, 0x539, 0xCE},
8698 {0x15, 0x546, 0xC9},
8699 {0x15, 0x70D, 0xB7},
8700 {0x15, 0x70E, 0x09},
8701 {0x15, 0x707, 0x10},
8702 {0x15, 0x70D, 0xAF},
8703 {0x15, 0x70E, 0x09},
8704 {0x15, 0x707, 0x01},
8705 {0x15, 0x707, 0x05},
8706 {0x15, 0x70D, 0x73},
8707 {0x15, 0x70E, 0x09},
8708 {0x15, 0x707, 0x14},
8709 {0x15, 0x6FF, 0xC4},
8713 static void ca0132_init_chip(struct hda_codec *codec)
8715 struct ca0132_spec *spec = codec->spec;
8720 mutex_init(&spec->chipio_mutex);
8729 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8730 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8732 snd_hda_codec_write(codec, codec->core.afg, 0,
8733 AC_VERB_SET_CODEC_RESET, 0);
8734 snd_hda_codec_write(codec, codec->core.afg, 0,
8735 AC_VERB_SET_CODEC_RESET, 0);
8738 spec->cur_out_type = SPEAKER_OUT;
8740 spec->cur_mic_type = DIGITAL_MIC;
8742 spec->cur_mic_type = REAR_MIC;
8744 spec->cur_mic_boost = 0;
8746 for (i = 0; i < VNODES_COUNT; i++) {
8747 spec->vnode_lvol[i] = 0x5a;
8748 spec->vnode_rvol[i] = 0x5a;
8749 spec->vnode_lswitch[i] = 0;
8750 spec->vnode_rswitch[i] = 0;
8757 for (i = 0; i < num_fx; i++) {
8758 on = (unsigned int)ca0132_effects[i].reqs[0];
8759 spec->effects_switch[i] = on ? 1 : 0;
8763 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8767 spec->speaker_range_val[0] = 1;
8768 spec->speaker_range_val[1] = 1;
8770 spec->xbass_xover_freq = 8;
8771 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8772 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8774 spec->bass_redirect_xover_freq = 8;
8777 spec->voicefx_val = 0;
8778 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8779 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8782 * The ZxR doesn't have a front panel header, and it's line-in is on
8784 * to make sure that spec->in_enum_val is set properly.
8787 spec->in_enum_val = REAR_MIC;
8790 ca0132_init_tuning_defaults(codec);
8798 static void r3di_gpio_shutdown(struct hda_codec *codec)
8800 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8806 static void sbz_region2_exit(struct hda_codec *codec)
8808 struct ca0132_spec *spec = codec->spec;
8811 for (i = 0; i < 4; i++)
8812 writeb(0x0, spec->mem_base + 0x100);
8813 for (i = 0; i < 8; i++)
8814 writeb(0xb3, spec->mem_base + 0x304);
8816 ca0113_mmio_gpio_set(codec, 0, false);
8817 ca0113_mmio_gpio_set(codec, 1, false);
8818 ca0113_mmio_gpio_set(codec, 4, true);
8819 ca0113_mmio_gpio_set(codec, 5, false);
8820 ca0113_mmio_gpio_set(codec, 7, false);
8823 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8825 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8828 snd_hda_codec_write(codec, 0x11, 0,
8829 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8831 for (i = 0; i < ARRAY_SIZE(pins); i++)
8832 snd_hda_codec_write(codec, pins[i], 0,
8833 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8836 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8838 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8841 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8842 snd_hda_codec_write(codec, pins[i], 0,
8843 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8848 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8851 if (dir >= 0)
8852 snd_hda_codec_write(codec, 0x01, 0,
8854 if (mask >= 0)
8855 snd_hda_codec_write(codec, 0x01, 0,
8858 if (data >= 0)
8859 snd_hda_codec_write(codec, 0x01, 0,
8863 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8865 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8868 for (i = 0; i < ARRAY_SIZE(pins); i++)
8869 snd_hda_codec_write(codec, pins[i], 0,
8870 AC_VERB_SET_POWER_STATE, 0x03);
8873 static void sbz_exit_chip(struct hda_codec *codec)
8875 chipio_set_stream_control(codec, 0x03, 0);
8876 chipio_set_stream_control(codec, 0x04, 0);
8879 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8880 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8881 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8883 chipio_set_stream_control(codec, 0x14, 0);
8884 chipio_set_stream_control(codec, 0x0C, 0);
8886 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8887 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8889 chipio_write(codec, 0x18a020, 0x00000083);
8891 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8892 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8893 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8895 chipio_set_stream_control(codec, 0x0C, 0);
8897 chipio_set_control_param(codec, 0x0D, 0x24);
8899 ca0132_clear_unsolicited(codec);
8900 sbz_set_pin_ctl_default(codec);
8902 snd_hda_codec_write(codec, 0x0B, 0,
8903 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8905 sbz_region2_exit(codec);
8908 static void r3d_exit_chip(struct hda_codec *codec)
8910 ca0132_clear_unsolicited(codec);
8911 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8912 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8915 static void ae5_exit_chip(struct hda_codec *codec)
8917 chipio_set_stream_control(codec, 0x03, 0);
8918 chipio_set_stream_control(codec, 0x04, 0);
8920 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8921 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8922 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8923 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8924 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8925 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8926 ca0113_mmio_gpio_set(codec, 0, false);
8927 ca0113_mmio_gpio_set(codec, 1, false);
8929 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8930 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8932 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8934 chipio_set_stream_control(codec, 0x18, 0);
8935 chipio_set_stream_control(codec, 0x0c, 0);
8937 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8940 static void ae7_exit_chip(struct hda_codec *codec)
8942 chipio_set_stream_control(codec, 0x18, 0);
8943 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8944 chipio_set_stream_channels(codec, 0x21, 0);
8945 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8946 chipio_set_control_param(codec, 0x20, 0x01);
8948 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8950 chipio_set_stream_control(codec, 0x18, 0);
8951 chipio_set_stream_control(codec, 0x0c, 0);
8953 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8954 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8955 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8956 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8957 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8958 ca0113_mmio_gpio_set(codec, 0, false);
8959 ca0113_mmio_gpio_set(codec, 1, false);
8960 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8962 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8963 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8966 static void zxr_exit_chip(struct hda_codec *codec)
8968 chipio_set_stream_control(codec, 0x03, 0);
8969 chipio_set_stream_control(codec, 0x04, 0);
8970 chipio_set_stream_control(codec, 0x14, 0);
8971 chipio_set_stream_control(codec, 0x0C, 0);
8973 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8974 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8976 chipio_write(codec, 0x18a020, 0x00000083);
8978 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8979 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8981 ca0132_clear_unsolicited(codec);
8982 sbz_set_pin_ctl_default(codec);
8983 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8985 ca0113_mmio_gpio_set(codec, 5, false);
8986 ca0113_mmio_gpio_set(codec, 2, false);
8987 ca0113_mmio_gpio_set(codec, 3, false);
8988 ca0113_mmio_gpio_set(codec, 0, false);
8989 ca0113_mmio_gpio_set(codec, 4, true);
8990 ca0113_mmio_gpio_set(codec, 0, true);
8991 ca0113_mmio_gpio_set(codec, 5, true);
8992 ca0113_mmio_gpio_set(codec, 2, false);
8993 ca0113_mmio_gpio_set(codec, 3, false);
8996 static void ca0132_exit_chip(struct hda_codec *codec)
9000 if (dspload_is_loaded(codec))
9001 dsp_reset(codec);
9012 static void sbz_dsp_startup_check(struct hda_codec *codec)
9014 struct ca0132_spec *spec = codec->spec;
9016 unsigned int cur_address = 0x390;
9018 unsigned int failure = 0;
9021 if (spec->startup_check_entered)
9024 spec->startup_check_entered = true;
9026 for (i = 0; i < 4; i++) {
9027 chipio_read(codec, cur_address, &dsp_data_check[i]);
9028 cur_address += 0x4;
9030 for (i = 0; i < 4; i++) {
9031 if (dsp_data_check[i] == 0xa1a2a3a4)
9035 codec_dbg(codec, "Startup Check: %d ", failure);
9037 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9043 while (failure && (reload != 0)) {
9044 codec_info(codec, "Reloading... Tries left: %d", reload);
9045 sbz_exit_chip(codec);
9046 spec->dsp_state = DSP_DOWNLOAD_INIT;
9047 snd_hda_codec_init(codec);
9048 failure = 0;
9049 for (i = 0; i < 4; i++) {
9050 chipio_read(codec, cur_address, &dsp_data_check[i]);
9051 cur_address += 0x4;
9053 for (i = 0; i < 4; i++) {
9054 if (dsp_data_check[i] == 0xa1a2a3a4)
9057 reload--;
9061 codec_info(codec, "DSP fixed.");
9066 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9070 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9075 * to 0 just incase a value has lingered from a boot into Windows.
9077 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9079 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9080 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9081 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9082 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9083 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9084 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9085 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9086 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9092 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9094 struct ca0132_spec *spec = codec->spec;
9096 writel(0x00820680, spec->mem_base + 0x01C);
9097 writel(0x00820680, spec->mem_base + 0x01C);
9099 chipio_write(codec, 0x18b0a4, 0x000000c2);
9101 snd_hda_codec_write(codec, 0x11, 0,
9102 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9105 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9107 chipio_write(codec, 0x18b0a4, 0x000000c2);
9109 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9111 snd_hda_codec_write(codec, 0x11, 0,
9112 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9115 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9117 chipio_write(codec, 0x18b0a4, 0x000000c2);
9119 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9120 chipio_8051_write_exram(codec, 0x1920, 0x00);
9121 chipio_8051_write_exram(codec, 0x1921, 0x40);
9123 snd_hda_codec_write(codec, 0x11, 0,
9124 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9132 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9134 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9135 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9138 chipio_write(codec, 0x189000, 0x0001f100);
9140 chipio_write(codec, 0x18900c, 0x0001f100);
9145 * 0xfa92 in exram. This function seems to have something to do with
9149 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9151 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9154 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9156 chipio_write(codec, 0x18902c, 0x00000000);
9158 chipio_write(codec, 0x18902c, 0x00000003);
9161 for (i = 0; i < ARRAY_SIZE(addr); i++)
9162 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9171 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9172 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9176 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9177 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9178 0x000000c1, 0x00000080
9182 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9183 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9184 0x000000c1, 0x00000080
9188 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9189 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9190 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9191 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9195 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9196 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9197 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9198 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9199 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9200 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9201 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9202 0x00000080, 0x00880680
9205 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9207 struct ca0132_spec *spec = codec->spec;
9212 for (i = 0; i < 3; i++)
9213 writel(0x00000000, spec->mem_base + addr[i]);
9218 tmp[0] = 0x00880480;
9219 tmp[1] = 0x00000080;
9222 tmp[0] = 0x00820680;
9223 tmp[1] = 0x00000083;
9226 tmp[0] = 0x00880680;
9227 tmp[1] = 0x00000083;
9230 tmp[0] = 0x00000000;
9231 tmp[1] = 0x00000000;
9235 for (i = 0; i < 2; i++)
9236 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9251 for (i = 0; i < count; i++)
9252 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9255 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9257 struct ca0132_spec *spec = codec->spec;
9266 writel(0x00000680, spec->mem_base + 0x1c);
9267 writel(0x00880680, spec->mem_base + 0x1c);
9270 for (i = 0; i < count; i++) {
9272 * AE-7 shares all writes with the AE-5, except that it writes
9273 * a different value to 0x20c.
9276 writel(0x00800001, spec->mem_base + addr[i]);
9280 writel(data[i], spec->mem_base + addr[i]);
9284 writel(0x00880680, spec->mem_base + 0x1c);
9287 static void ca0132_mmio_init(struct hda_codec *codec)
9289 struct ca0132_spec *spec = codec->spec;
9295 ca0132_mmio_init_sbz(codec);
9298 ca0132_mmio_init_ae5(codec);
9306 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9307 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9311 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9312 0x01, 0x6b, 0x57
9317 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9320 static void ae5_register_set(struct hda_codec *codec)
9322 struct ca0132_spec *spec = codec->spec;
9330 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9332 chipio_8051_write_direct(codec, 0x93, 0x10);
9333 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9336 tmp[0] = 0x03;
9337 tmp[1] = 0x03;
9338 tmp[2] = 0x07;
9340 tmp[0] = 0x0f;
9341 tmp[1] = 0x0f;
9342 tmp[2] = 0x0f;
9345 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9346 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9352 for (i = 0; cur_addr < 12; i++, cur_addr++)
9353 writeb(data[i], spec->mem_base + addr[cur_addr]);
9356 writel(data[i], spec->mem_base + addr[cur_addr]);
9358 writel(0x00800001, spec->mem_base + 0x20c);
9361 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9362 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9364 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9367 chipio_8051_write_direct(codec, 0x90, 0x00);
9368 chipio_8051_write_direct(codec, 0x90, 0x10);
9371 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9379 static void ca0132_alt_init(struct hda_codec *codec)
9381 struct ca0132_spec *spec = codec->spec;
9383 ca0132_alt_vol_setup(codec);
9387 codec_dbg(codec, "SBZ alt_init");
9388 ca0132_gpio_init(codec);
9389 sbz_pre_dsp_setup(codec);
9390 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9391 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9394 codec_dbg(codec, "R3DI alt_init");
9395 ca0132_gpio_init(codec);
9396 ca0132_gpio_setup(codec);
9397 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9398 r3di_pre_dsp_setup(codec);
9399 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9403 r3d_pre_dsp_setup(codec);
9404 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9405 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9408 ca0132_gpio_init(codec);
9409 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9410 chipio_write(codec, 0x18b030, 0x00000020);
9411 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9412 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9413 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9416 ca0132_gpio_init(codec);
9417 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9418 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9419 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9420 chipio_write(codec, 0x18b008, 0x000000f8);
9421 chipio_write(codec, 0x18b008, 0x000000f0);
9422 chipio_write(codec, 0x18b030, 0x00000020);
9423 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9426 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9427 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9428 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9429 zxr_pre_dsp_setup(codec);
9436 static int ca0132_init(struct hda_codec *codec)
9438 struct ca0132_spec *spec = codec->spec;
9439 struct auto_pin_cfg *cfg = &spec->autocfg;
9445 * there's only two reasons for it. One, the codec has awaken from a
9453 if (spec->dsp_state == DSP_DOWNLOADED) {
9454 dsp_loaded = dspload_is_loaded(codec);
9456 spec->dsp_reload = true;
9457 spec->dsp_state = DSP_DOWNLOAD_INIT;
9460 sbz_dsp_startup_check(codec);
9461 return 0;
9465 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9466 spec->dsp_state = DSP_DOWNLOAD_INIT;
9467 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9470 ca0132_mmio_init(codec);
9472 CLASS(snd_hda_power_pm, pm)(codec);
9475 ae5_register_set(codec);
9477 ca0132_init_params(codec);
9478 ca0132_init_flags(codec);
9480 snd_hda_sequence_write(codec, spec->base_init_verbs);
9483 ca0132_alt_init(codec);
9485 ca0132_download_dsp(codec);
9487 ca0132_refresh_widget_caps(codec);
9492 r3d_setup_defaults(codec);
9496 sbz_setup_defaults(codec);
9499 ae5_setup_defaults(codec);
9502 ae7_setup_defaults(codec);
9505 ca0132_setup_defaults(codec);
9506 ca0132_init_analog_mic2(codec);
9507 ca0132_init_dmic(codec);
9511 for (i = 0; i < spec->num_outputs; i++)
9512 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9514 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9516 for (i = 0; i < spec->num_inputs; i++)
9517 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9519 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9522 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9523 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9524 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9525 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9526 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9530 ca0132_gpio_setup(codec);
9532 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9534 ca0132_alt_select_out(codec);
9535 ca0132_alt_select_in(codec);
9537 ca0132_select_out(codec);
9538 ca0132_select_mic(codec);
9541 snd_hda_jack_report_sync(codec);
9547 if (spec->dsp_reload) {
9548 spec->dsp_reload = false;
9549 ca0132_pe_switch_set(codec);
9552 return 0;
9555 static int dbpro_init(struct hda_codec *codec)
9557 struct ca0132_spec *spec = codec->spec;
9558 struct auto_pin_cfg *cfg = &spec->autocfg;
9561 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9562 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9564 for (i = 0; i < spec->num_inputs; i++)
9565 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9567 return 0;
9570 static void ca0132_free(struct hda_codec *codec)
9572 struct ca0132_spec *spec = codec->spec;
9574 cancel_delayed_work_sync(&spec->unsol_hp_work);
9575 snd_hda_power_up(codec);
9578 sbz_exit_chip(codec);
9581 zxr_exit_chip(codec);
9584 r3d_exit_chip(codec);
9587 ae5_exit_chip(codec);
9590 ae7_exit_chip(codec);
9593 r3di_gpio_shutdown(codec);
9599 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9600 ca0132_exit_chip(codec);
9602 snd_hda_power_down(codec);
9604 if (spec->mem_base)
9605 pci_iounmap(codec->bus->pci, spec->mem_base);
9607 kfree(spec->spec_init_verbs);
9608 kfree(codec->spec);
9611 static void dbpro_free(struct hda_codec *codec)
9613 struct ca0132_spec *spec = codec->spec;
9615 zxr_dbpro_power_state_shutdown(codec);
9617 kfree(spec->spec_init_verbs);
9618 kfree(codec->spec);
9621 static void ca0132_config(struct hda_codec *codec)
9623 struct ca0132_spec *spec = codec->spec;
9625 spec->dacs[0] = 0x2;
9626 spec->dacs[1] = 0x3;
9627 spec->dacs[2] = 0x4;
9629 spec->multiout.dac_nids = spec->dacs;
9630 spec->multiout.num_dacs = 3;
9633 spec->multiout.max_channels = 2;
9635 spec->multiout.max_channels = 6;
9639 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9640 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9643 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9644 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9647 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9648 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9651 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9652 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9655 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9656 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9659 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9660 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9663 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9664 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9672 spec->num_outputs = 2;
9673 spec->out_pins[0] = 0x0b; /* speaker out */
9674 spec->out_pins[1] = 0x0f;
9675 spec->shared_out_nid = 0x2;
9676 spec->unsol_tag_hp = 0x0f;
9678 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9679 spec->adcs[1] = 0x8; /* analog mic2 */
9680 spec->adcs[2] = 0xa; /* what u hear */
9682 spec->num_inputs = 3;
9683 spec->input_pins[0] = 0x12;
9684 spec->input_pins[1] = 0x11;
9685 spec->input_pins[2] = 0x13;
9686 spec->shared_mic_nid = 0x7;
9687 spec->unsol_tag_amic1 = 0x11;
9691 spec->num_outputs = 2;
9692 spec->out_pins[0] = 0x0B; /* Line out */
9693 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9694 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9695 spec->out_pins[3] = 0x11; /* Rear surround */
9696 spec->shared_out_nid = 0x2;
9697 spec->unsol_tag_hp = spec->out_pins[1];
9698 spec->unsol_tag_front_hp = spec->out_pins[2];
9700 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9701 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9702 spec->adcs[2] = 0xa; /* what u hear */
9704 spec->num_inputs = 2;
9705 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9706 spec->input_pins[1] = 0x13; /* What U Hear */
9707 spec->shared_mic_nid = 0x7;
9708 spec->unsol_tag_amic1 = spec->input_pins[0];
9711 spec->dig_out = 0x05;
9712 spec->multiout.dig_out_nid = spec->dig_out;
9713 spec->dig_in = 0x09;
9716 spec->num_outputs = 2;
9717 spec->out_pins[0] = 0x0B; /* Line out */
9718 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9719 spec->out_pins[2] = 0x10; /* Center/LFE */
9720 spec->out_pins[3] = 0x11; /* Rear surround */
9721 spec->shared_out_nid = 0x2;
9722 spec->unsol_tag_hp = spec->out_pins[1];
9723 spec->unsol_tag_front_hp = spec->out_pins[2];
9725 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9726 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9727 spec->adcs[2] = 0xa; /* what u hear */
9729 spec->num_inputs = 2;
9730 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9731 spec->input_pins[1] = 0x13; /* What U Hear */
9732 spec->shared_mic_nid = 0x7;
9733 spec->unsol_tag_amic1 = spec->input_pins[0];
9736 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9738 spec->num_inputs = 1;
9739 spec->input_pins[0] = 0x11; /* RCA Line-in */
9741 spec->dig_out = 0x05;
9742 spec->multiout.dig_out_nid = spec->dig_out;
9744 spec->dig_in = 0x09;
9748 spec->num_outputs = 2;
9749 spec->out_pins[0] = 0x0B; /* Line out */
9750 spec->out_pins[1] = 0x11; /* Rear headphone out */
9751 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9752 spec->out_pins[3] = 0x0F; /* Rear surround */
9753 spec->shared_out_nid = 0x2;
9754 spec->unsol_tag_hp = spec->out_pins[1];
9755 spec->unsol_tag_front_hp = spec->out_pins[2];
9757 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9758 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9759 spec->adcs[2] = 0xa; /* what u hear */
9761 spec->num_inputs = 2;
9762 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9763 spec->input_pins[1] = 0x13; /* What U Hear */
9764 spec->shared_mic_nid = 0x7;
9765 spec->unsol_tag_amic1 = spec->input_pins[0];
9768 spec->dig_out = 0x05;
9769 spec->multiout.dig_out_nid = spec->dig_out;
9772 spec->num_outputs = 2;
9773 spec->out_pins[0] = 0x0B; /* Line out */
9774 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9775 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9776 spec->out_pins[3] = 0x11; /* Rear surround */
9777 spec->shared_out_nid = 0x2;
9778 spec->unsol_tag_hp = spec->out_pins[1];
9779 spec->unsol_tag_front_hp = spec->out_pins[2];
9781 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9782 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9783 spec->adcs[2] = 0x0a; /* what u hear */
9785 spec->num_inputs = 2;
9786 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9787 spec->input_pins[1] = 0x13; /* What U Hear */
9788 spec->shared_mic_nid = 0x7;
9789 spec->unsol_tag_amic1 = spec->input_pins[0];
9792 spec->dig_out = 0x05;
9793 spec->multiout.dig_out_nid = spec->dig_out;
9796 spec->num_outputs = 2;
9797 spec->out_pins[0] = 0x0b; /* speaker out */
9798 spec->out_pins[1] = 0x10; /* headphone out */
9799 spec->shared_out_nid = 0x2;
9800 spec->unsol_tag_hp = spec->out_pins[1];
9802 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9803 spec->adcs[1] = 0x8; /* analog mic2 */
9804 spec->adcs[2] = 0xa; /* what u hear */
9806 spec->num_inputs = 3;
9807 spec->input_pins[0] = 0x12;
9808 spec->input_pins[1] = 0x11;
9809 spec->input_pins[2] = 0x13;
9810 spec->shared_mic_nid = 0x7;
9811 spec->unsol_tag_amic1 = spec->input_pins[0];
9814 spec->dig_out = 0x05;
9815 spec->multiout.dig_out_nid = spec->dig_out;
9816 spec->dig_in = 0x09;
9821 static int ca0132_prepare_verbs(struct hda_codec *codec)
9825 struct ca0132_spec *spec = codec->spec;
9827 spec->chip_init_verbs = ca0132_init_verbs0;
9833 spec->desktop_init_verbs = ca0132_init_verbs1;
9834 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9837 if (!spec->spec_init_verbs)
9838 return -ENOMEM;
9841 spec->spec_init_verbs[0].nid = 0x0b;
9842 spec->spec_init_verbs[0].param = 0x78D;
9843 spec->spec_init_verbs[0].verb = 0x00;
9847 spec->spec_init_verbs[2].nid = 0x0b;
9848 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9849 spec->spec_init_verbs[2].verb = 0x02;
9851 spec->spec_init_verbs[3].nid = 0x10;
9852 spec->spec_init_verbs[3].param = 0x78D;
9853 spec->spec_init_verbs[3].verb = 0x02;
9855 spec->spec_init_verbs[4].nid = 0x10;
9856 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9857 spec->spec_init_verbs[4].verb = 0x02;
9860 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9861 return 0;
9866 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9870 static void sbz_detect_quirk(struct hda_codec *codec)
9872 switch (codec->core.subsystem_id) {
9873 case 0x11020033:
9874 codec->fixup_id = QUIRK_ZXR;
9876 case 0x1102003f:
9877 codec->fixup_id = QUIRK_ZXR_DBPRO;
9880 codec->fixup_id = QUIRK_SBZ;
9885 static void ca0132_codec_remove(struct hda_codec *codec)
9887 struct ca0132_spec *spec = codec->spec;
9890 return dbpro_free(codec);
9892 return ca0132_free(codec);
9895 static int ca0132_codec_probe(struct hda_codec *codec,
9901 codec_dbg(codec, "%s\n", __func__);
9905 return -ENOMEM;
9906 codec->spec = spec;
9907 spec->codec = codec;
9909 /* Detect codec quirk */
9910 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL);
9912 sbz_detect_quirk(codec);
9914 codec->pcm_format_first = 1;
9915 codec->no_sticky_stream = 1;
9918 spec->dsp_state = DSP_DOWNLOAD_INIT;
9919 spec->num_mixers = 1;
9924 spec->mixers[0] = desktop_mixer;
9925 snd_hda_codec_set_name(codec, "Sound Blaster Z");
9928 spec->mixers[0] = desktop_mixer;
9929 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9934 spec->mixers[0] = desktop_mixer;
9935 snd_hda_codec_set_name(codec, "Recon3D");
9938 spec->mixers[0] = r3di_mixer;
9939 snd_hda_codec_set_name(codec, "Recon3Di");
9942 spec->mixers[0] = desktop_mixer;
9943 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9946 spec->mixers[0] = desktop_mixer;
9947 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9950 spec->mixers[0] = ca0132_mixer;
9961 spec->use_alt_controls = true;
9962 spec->use_alt_functions = true;
9963 spec->use_pci_mmio = true;
9966 spec->use_alt_controls = true;
9967 spec->use_alt_functions = true;
9968 spec->use_pci_mmio = false;
9971 spec->use_alt_controls = false;
9972 spec->use_alt_functions = false;
9973 spec->use_pci_mmio = false;
9978 if (spec->use_pci_mmio) {
9979 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9980 if (spec->mem_base == NULL) {
9981 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9982 codec->fixup_id = QUIRK_NONE;
9987 spec->base_init_verbs = ca0132_base_init_verbs;
9988 spec->base_exit_verbs = ca0132_base_exit_verbs;
9990 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9992 ca0132_init_chip(codec);
9994 ca0132_config(codec);
9996 err = ca0132_prepare_verbs(codec);
9997 if (err < 0)
10000 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10001 if (err < 0)
10004 ca0132_setup_unsol(codec);
10006 return 0;
10009 ca0132_codec_remove(codec);
10013 static int ca0132_codec_build_controls(struct hda_codec *codec)
10015 struct ca0132_spec *spec = codec->spec;
10018 return dbpro_build_controls(codec);
10020 return ca0132_build_controls(codec);
10023 static int ca0132_codec_build_pcms(struct hda_codec *codec)
10025 struct ca0132_spec *spec = codec->spec;
10028 return dbpro_build_pcms(codec);
10030 return ca0132_build_pcms(codec);
10033 static int ca0132_codec_init(struct hda_codec *codec)
10035 struct ca0132_spec *spec = codec->spec;
10038 return dbpro_init(codec);
10040 return ca0132_init(codec);
10043 static int ca0132_codec_suspend(struct hda_codec *codec)
10045 struct ca0132_spec *spec = codec->spec;
10047 cancel_delayed_work_sync(&spec->unsol_hp_work);
10048 return 0;
10065 HDA_CODEC_ID(0x11020011, "CA0132"),
10071 MODULE_DESCRIPTION("Creative Sound Core3D codec");