Lines Matching +full:0 +full:x44200000
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x80
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
70 #define SCP_SET 0
107 #define VNODE_START_NID 0x80
117 #define EFFECT_START_NID 0x90
170 #define DSP_CAPTURE_INIT_LATENCY 0
181 int direct; /* 0:output; 1:input*/
187 #define EFX_DIR_OUT 0
193 .mid = 0x96,
194 .reqs = {0, 1},
197 .def_vals = {0x3F800000, 0x3F2B851F}
201 .mid = 0x96,
205 .def_vals = {0x3F800000, 0x3F266666}
209 .mid = 0x96,
213 .def_vals = {0x00000000, 0x3F000000}
217 .mid = 0x96,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
225 .mid = 0x96,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
233 .mid = 0x96,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
252 .mid = 0x95,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
260 .mid = 0x95,
264 .def_vals = {0x00000000, 0x3F3D70A4}
268 .mid = 0x95,
272 .def_vals = {0x3F800000, 0x3F000000}
276 .mid = 0x95,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
290 #define TUNING_CTL_START_NID 0xC0
313 int direct; /* 0:output; 1:input*/
321 .mid = 0x95,
324 .def_val = 0x41F00000
329 .mid = 0x95,
332 .def_val = 0x3F3D70A4
337 .mid = 0x96,
340 .def_val = 0x00000000
345 .mid = 0x96,
348 .def_val = 0x00000000
353 .mid = 0x96,
356 .def_val = 0x00000000
361 .mid = 0x96,
364 .def_val = 0x00000000
369 .mid = 0x96,
372 .def_val = 0x00000000
377 .mid = 0x96,
380 .def_val = 0x00000000
385 .mid = 0x96,
388 .def_val = 0x00000000
393 .mid = 0x96,
396 .def_val = 0x00000000
401 .mid = 0x96,
404 .def_val = 0x00000000
409 .mid = 0x96,
412 .def_val = 0x00000000
435 .mid = 0x95,
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
531 .mid = 0x96,
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
619 * module ID 0x96, the output effects module.
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
709 #define DSP_VOL_OUT 0
720 .mid = 0x32,
724 .mid = 0x37,
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
781 .val = 0xa0
784 .val = 0xc0
787 .val = 0x80
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
895 CONTROL_FLAG_C_MGR = 0,
952 /* 0: None, 1: Mic1In*/
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1040 SR_COUNT = 0x10,
1042 SR_RATE_UNKNOWN = 0x1F
1047 DSP_DOWNLOAD_INIT = 0,
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1194 { 0x0c, 0x411111f0 }, /* N/A */
1195 { 0x0d, 0x411111f0 }, /* N/A */
1196 { 0x0e, 0x411111f0 }, /* N/A */
1197 { 0x0f, 0x0321101f }, /* HP */
1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1199 { 0x11, 0x03a11021 }, /* Mic */
1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1201 { 0x13, 0x411111f0 }, /* N/A */
1202 { 0x18, 0x411111f0 }, /* N/A */
1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1210 { 0x0d, 0x014510f0 }, /* Digital Out */
1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1216 { 0x13, 0x908700f0 }, /* What U Hear In*/
1217 { 0x18, 0x50d000f0 }, /* N/A */
1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1225 { 0x0d, 0x014510f0 }, /* Digital Out */
1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1231 { 0x13, 0x908700f0 }, /* What U Hear In*/
1232 { 0x18, 0x50d000f0 }, /* N/A */
1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1240 { 0x0d, 0x014510f0 }, /* Digital Out */
1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1246 { 0x13, 0x908700f0 }, /* What U Hear In*/
1247 { 0x18, 0x50d000f0 }, /* N/A */
1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1255 { 0x0d, 0x014510f0 }, /* Digital Out */
1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1261 { 0x13, 0x908700f0 }, /* What U Hear In*/
1262 { 0x18, 0x50d000f0 }, /* N/A */
1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1270 { 0x0d, 0x014510f0 }, /* Digital Out */
1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1276 { 0x13, 0x908700f0 }, /* What U Hear In*/
1277 { 0x18, 0x500000f0 }, /* N/A */
1282 { 0x0b, 0x01017010 },
1283 { 0x0c, 0x014510f0 },
1284 { 0x0d, 0x414510f0 },
1285 { 0x0e, 0x01c520f0 },
1286 { 0x0f, 0x01017114 },
1287 { 0x10, 0x01017011 },
1288 { 0x11, 0x018170ff },
1289 { 0x12, 0x01a170f0 },
1290 { 0x13, 0x908700f0 },
1291 { 0x18, 0x500000f0 },
1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1335 unsigned int dac2port; /* ParamID 0x0d value. */
1370 { .dac2port = 0x24,
1374 .mmio_gpio_count = 0,
1375 .scp_cmds_count = 0,
1379 { .dac2port = 0x21,
1382 .hda_gpio_set = 0,
1383 .mmio_gpio_count = 0,
1384 .scp_cmds_count = 0,
1393 { .dac2port = 0x24,
1398 .scp_cmds_count = 0,
1402 { .dac2port = 0x21,
1406 .mmio_gpio_set = { 0 },
1407 .scp_cmds_count = 0,
1416 { .dac2port = 0x18,
1420 .mmio_gpio_set = { 0, 1, 1 },
1421 .scp_cmds_count = 0,
1424 { .dac2port = 0x12,
1428 .mmio_gpio_set = { 1, 1, 0 },
1429 .scp_cmds_count = 0,
1438 { .dac2port = 0x24,
1442 .mmio_gpio_set = { 1, 1, 0 },
1443 .scp_cmds_count = 0,
1447 { .dac2port = 0x21,
1451 .mmio_gpio_set = { 0, 1, 1 },
1452 .scp_cmds_count = 0,
1461 { .dac2port = 0xa4,
1463 .mmio_gpio_count = 0,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000012
1474 { .dac2port = 0xa1,
1476 .mmio_gpio_count = 0,
1478 .scp_cmd_mid = { 0x96, 0x96 },
1483 .chipio_write_addr = 0x0018b03c,
1484 .chipio_write_data = 0x00000012
1492 { .dac2port = 0x58,
1495 .mmio_gpio_pin = { 0 },
1498 .scp_cmd_mid = { 0x96, 0x96 },
1503 .chipio_write_addr = 0x0018b03c,
1504 .chipio_write_data = 0x00000000
1507 { .dac2port = 0x58,
1510 .mmio_gpio_pin = { 0 },
1513 .scp_cmd_mid = { 0x96, 0x96 },
1518 .chipio_write_addr = 0x0018b03c,
1519 .chipio_write_data = 0x00000010
1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1534 return ((response == -1) ? -1 : 0);
1541 converter_format & 0xffff, res);
1548 unsigned char converter_stream_channel = 0;
1550 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1568 return 0;
1585 return 0;
1589 chip_addx & 0xffff);
1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1622 (spec->curr_chip_addx + 4) : ~0U;
1633 int status = 0;
1640 while ((count-- != 0) && (status == 0))
1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1667 0);
1673 (spec->curr_chip_addx + 4) : ~0U;
1691 if (err < 0)
1709 if (err < 0)
1713 if (err < 0)
1734 if (status < 0)
1754 if (err < 0)
1770 flag_bit = (flag_state ? 1 : 0);
1772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1791 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1812 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1815 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1819 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1872 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1903 * 0x80-0xFF.
1911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1916 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1917 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1919 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1927 tmp = addr & 0xff;
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1932 tmp = (addr >> 8) & 0xff;
1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1941 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1946 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1947 VENDOR_CHIPIO_8051_DATA_READ, 0);
1954 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1955 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1991 chipio_8051_set_address(codec, addr & 0xff);
1998 chipio_8051_set_address(codec, addr & 0xff);
2011 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2012 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2013 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2027 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2028 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2045 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2046 VENDOR_DSPIO_STATUS, 0);
2066 scp_data & 0xffff);
2067 if (status < 0)
2072 if (status < 0)
2076 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2077 VENDOR_DSPIO_STATUS, 0);
2080 -EIO : 0;
2089 int status = 0;
2095 count = 0;
2098 if (status != 0)
2110 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2114 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2119 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2120 VENDOR_DSPIO_SCP_READ_DATA, 0);
2122 return 0;
2128 int status = 0;
2137 count = 0;
2140 if (status != 0)
2146 if (status == 0) {
2149 if (status != 0)
2168 unsigned int header = 0;
2170 header = (data_size & 0x1f) << 27;
2171 header |= (error_flag & 0x01) << 26;
2172 header |= (resp_flag & 0x01) << 25;
2173 header |= (device_flag & 0x01) << 24;
2174 header |= (req & 0x7f) << 17;
2175 header |= (get_flag & 0x01) << 16;
2176 header |= (source_id & 0xff) << 8;
2177 header |= target_id & 0xff;
2193 *data_size = (header >> 27) & 0x1f;
2195 *error_flag = (header >> 26) & 0x01;
2197 *resp_flag = (header >> 25) & 0x01;
2199 *device_flag = (header >> 24) & 0x01;
2201 *req = (header >> 17) & 0x7f;
2203 *get_flag = (header >> 16) & 0x01;
2205 *source_id = (header >> 8) & 0xff;
2207 *target_id = header & 0xff;
2221 unsigned int dummy = 0;
2227 } while (status == 0 && time_before(jiffies, timeout));
2233 unsigned int data = 0;
2236 if (dspio_read(codec, &data) < 0)
2239 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2245 return 0;
2263 unsigned int scp_send_size = 0;
2272 *bytes_returned = 0;
2293 spec->wait_scp_header &= 0xffff0000;
2302 if (status < 0) {
2303 spec->wait_scp = 0;
2309 memset(return_buf, 0, return_buf_size);
2320 status = 0;
2324 spec->wait_scp = 0;
2348 int status = 0;
2354 memset(&scp_send, 0, sizeof(scp_send));
2355 memset(&scp_reply, 0, sizeof(scp_reply));
2357 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2365 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2371 0, 0, 0, len/sizeof(unsigned int));
2372 if (data != NULL && len > 0) {
2377 ret_bytes = 0;
2383 if (status < 0) {
2396 return 0;
2436 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2445 int status = 0;
2449 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2450 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2453 if (status < 0) {
2458 if ((*dma_chan + 1) == 0) {
2474 int status = 0;
2475 unsigned int dummy = 0;
2480 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2484 if (status < 0) {
2504 if (err < 0)
2510 if (halt_state != 0) {
2515 if (err < 0)
2522 if (err < 0)
2526 return 0;
2539 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2548 return 0;
2582 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2591 int status = 0;
2617 active = 0;
2625 if (status < 0) {
2640 if (status < 0) {
2650 if (status < 0) {
2661 if (status < 0) {
2670 if (status < 0) {
2678 if (status < 0) {
2685 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2686 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2692 return 0;
2703 int status = 0;
2710 unsigned int dma_cfg = 0;
2711 unsigned int adr_ofs = 0;
2712 unsigned int xfr_cnt = 0;
2732 incr_field = 0;
2745 if (status < 0) {
2752 (code ? 0 : 1));
2756 if (status < 0) {
2770 if (status < 0) {
2777 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2778 "ADROFS=0x%x, XFRCNT=0x%x\n",
2783 return 0;
2792 unsigned int reg = 0;
2793 int status = 0;
2801 if (status < 0) {
2813 if (status < 0) {
2828 unsigned int reg = 0;
2829 int status = 0;
2837 if (status < 0) {
2848 if (status < 0) {
2874 int status = 0;
2878 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2879 if (status < 0)
2886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2890 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2894 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2895 if (status < 0)
2898 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2899 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2903 return (res < 0) ? res : 0;
2911 int status = 0;
2913 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2914 if (status < 0)
2917 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2921 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2943 rate_multi, 0, port_map);
2956 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2980 if (status < 0) {
3001 DMA_STATE_STOP = 0,
3017 return 0;
3036 if (status < 0)
3039 return 0;
3054 return 0;
3058 return 0;
3076 return 0;
3101 static const u32 g_magic_value = 0x4c46584d;
3102 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3116 return p->count == 0;
3133 #define INVALID_DMA_CHANNEL (~0U)
3155 status = chipio_write(codec, data[0], data[1]);
3156 if (status < 0) {
3163 return 0;
3171 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3188 int status = 0;
3220 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3230 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3232 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3252 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3256 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3259 if (hda_frame_size_words == 0) {
3269 "chpadr=0x%08x frmsz=%u nchan=%u "
3287 while (words_to_write != 0) {
3294 if (status < 0)
3298 if (status < 0)
3305 if (status < 0)
3308 if (status < 0)
3315 if (status < 0)
3317 if (remainder_words != 0) {
3322 if (status < 0)
3324 remainder_words = 0;
3328 if (status < 0)
3347 if (status < 0)
3355 if (remainder_words != 0) {
3368 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3385 unsigned short hda_format = 0;
3387 unsigned char stream_id = 0;
3411 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3416 if (status < 0) {
3425 if (status < 0)
3431 if (status < 0) {
3438 port_map_mask = 0;
3441 if (status < 0) {
3448 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3449 if (status < 0) {
3463 if (status < 0)
3473 if (port_map_mask != 0)
3476 if (status < 0)
3480 WIDGET_CHIP_CTRL, 0, 0, &response);
3503 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3504 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3507 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3517 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3520 * @router_chans: number of audio router channels to be allocated (0 means use
3536 int status = 0;
3541 if (router_chans == 0) {
3561 if (status < 0)
3568 if (status < 0)
3578 } while (0);
3586 unsigned int data = 0;
3587 int status = 0;
3589 status = chipio_read(codec, 0x40004, &data);
3590 if ((status < 0) || (data != 1))
3623 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3636 gpio_data = gpio_pin & 0xF;
3637 gpio_data |= ((enable << 8) & 0x100);
3639 writew(gpio_data, spec->mem_base + 0x320);
3656 writel(0x0000007e, spec->mem_base + 0x210);
3657 readl(spec->mem_base + 0x210);
3658 writel(0x0000005a, spec->mem_base + 0x210);
3659 readl(spec->mem_base + 0x210);
3660 readl(spec->mem_base + 0x210);
3662 writel(0x00800005, spec->mem_base + 0x20c);
3663 writel(group, spec->mem_base + 0x804);
3665 writel(0x00800005, spec->mem_base + 0x20c);
3666 write_val = (target & 0xff);
3670 writel(write_val, spec->mem_base + 0x204);
3676 readl(spec->mem_base + 0x860);
3677 readl(spec->mem_base + 0x854);
3678 readl(spec->mem_base + 0x840);
3680 writel(0x00800004, spec->mem_base + 0x20c);
3681 writel(0x00000000, spec->mem_base + 0x210);
3682 readl(spec->mem_base + 0x210);
3683 readl(spec->mem_base + 0x210);
3695 writel(0x0000007e, spec->mem_base + 0x210);
3696 readl(spec->mem_base + 0x210);
3697 writel(0x0000005a, spec->mem_base + 0x210);
3698 readl(spec->mem_base + 0x210);
3699 readl(spec->mem_base + 0x210);
3701 writel(0x00800003, spec->mem_base + 0x20c);
3702 writel(group, spec->mem_base + 0x804);
3704 writel(0x00800005, spec->mem_base + 0x20c);
3705 write_val = (target & 0xff);
3709 writel(write_val, spec->mem_base + 0x204);
3711 readl(spec->mem_base + 0x860);
3712 readl(spec->mem_base + 0x854);
3713 readl(spec->mem_base + 0x840);
3715 writel(0x00800004, spec->mem_base + 0x20c);
3716 writel(0x00000000, spec->mem_base + 0x210);
3717 readl(spec->mem_base + 0x210);
3718 readl(spec->mem_base + 0x210);
3737 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3738 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3739 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3742 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3743 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3758 snd_hda_codec_write(codec, 0x01, 0,
3759 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3760 snd_hda_codec_write(codec, 0x01, 0,
3761 AC_VERB_SET_GPIO_MASK, 0x07);
3762 snd_hda_codec_write(codec, 0x01, 0,
3763 AC_VERB_SET_GPIO_DATA, 0x04);
3764 snd_hda_codec_write(codec, 0x01, 0,
3765 AC_VERB_SET_GPIO_DATA, 0x06);
3768 snd_hda_codec_write(codec, 0x01, 0,
3769 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3770 snd_hda_codec_write(codec, 0x01, 0,
3771 AC_VERB_SET_GPIO_MASK, 0x1F);
3772 snd_hda_codec_write(codec, 0x01, 0,
3773 AC_VERB_SET_GPIO_DATA, 0x0C);
3785 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3787 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3802 /* Set GPIO bit 1 to 0 for rear mic */
3803 R3DI_REAR_MIC = 0,
3809 /* Set GPIO bit 2 to 0 for headphone */
3810 R3DI_HEADPHONE_OUT = 0,
3816 R3DI_DSP_DOWNLOADING = 0,
3828 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3838 snd_hda_codec_write(codec, codec->core.afg, 0,
3848 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3853 snd_hda_codec_write(codec, codec->core.afg, 0,
3857 /* Set DOWNLOADING bit to 0. */
3860 snd_hda_codec_write(codec, codec->core.afg, 0,
3867 snd_hda_codec_write(codec, codec->core.afg, 0,
3882 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3884 return 0;
3894 return 0;
3901 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3903 return 0;
3915 return 0;
3979 stream_tag, 0, format);
3981 return 0;
3991 return 0;
3994 return 0;
4006 return 0;
4032 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4050 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4059 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4079 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4080 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4081 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4082 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4083 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4084 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4085 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4086 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4087 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4088 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4089 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4090 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4091 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4092 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4093 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4094 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4095 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4099 * This table counts from float 0 to 1 in increments of .01, which is
4103 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4104 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4105 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4106 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4107 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4108 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4109 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4110 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4111 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4112 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4113 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4114 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4115 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4116 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4117 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4118 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4119 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4127 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4128 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4129 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4130 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4131 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4132 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4133 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4134 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4135 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4136 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4137 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4138 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4139 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4140 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4141 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4142 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4143 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4150 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4151 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4152 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4153 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4154 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4155 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4156 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4157 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4158 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4159 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4160 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4161 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4162 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4163 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4164 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4165 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4166 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4167 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4168 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4169 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4170 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4171 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4172 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4173 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4174 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4175 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4176 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4180 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4181 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4182 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4183 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4184 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4185 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4186 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4187 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4188 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4189 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4190 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4191 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4192 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4193 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4194 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4195 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4196 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4200 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4201 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4202 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4203 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4204 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4205 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4206 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4207 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4208 0x41C00000
4216 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4219 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4239 return 0;
4252 return 0;
4267 return 0;
4283 uinfo->value.integer.min = 0;
4287 return 0;
4302 return 0;
4309 return 0;
4318 uinfo->value.integer.min = 0;
4322 return 0;
4337 return 0;
4347 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4348 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4357 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4382 return 0;
4385 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4395 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4401 if (err < 0)
4405 return 0;
4418 /* EQ defaults to 0dB. */
4460 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4461 if (err < 0)
4465 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4466 if (err < 0)
4470 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4471 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4472 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4473 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4474 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4475 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4476 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4477 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4480 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4481 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4485 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4486 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4487 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4493 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4494 if (err < 0)
4498 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4499 if (err < 0)
4503 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4504 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4505 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4506 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4507 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4508 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4509 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4510 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4513 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4514 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4515 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4518 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4519 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4524 return 0;
4542 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4558 return 0;
4561 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4562 err = dspio_set_uint_param(codec, 0x96,
4564 if (err < 0)
4569 err = dspio_set_uint_param(codec, 0x96,
4571 if (err < 0)
4574 err = dspio_set_uint_param(codec, 0x96,
4576 if (err < 0)
4584 err = dspio_set_uint_param(codec, 0x96,
4586 if (err < 0)
4590 return 0;
4606 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4607 if (err < 0)
4613 err = dspio_set_uint_param(codec, 0x96,
4615 if (err < 0)
4619 return 0;
4634 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4652 return 0;
4659 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4660 AC_VERB_GET_GPIO_DATA, 0);
4667 snd_hda_codec_write(codec, codec->core.afg, 0,
4672 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4679 for (i = 0; i < out_info->scp_cmds_count; i++) {
4684 if (err < 0)
4689 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4701 zxr_headphone_gain_set(codec, 0);
4712 return 0;
4720 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4721 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4771 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4772 if (err < 0)
4776 if (err < 0)
4784 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4785 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4788 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4790 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4792 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4794 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4806 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4807 if (err < 0)
4813 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4814 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4817 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4818 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4819 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4830 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4832 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4834 if (err < 0)
4847 /* Set speaker EQ bypass attenuation to 0. */
4848 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4849 if (err < 0)
4856 err = dspio_set_uint_param(codec, 0x96,
4858 if (err < 0)
4865 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4866 if (err < 0)
4870 err = dspio_set_uint_param(codec, 0x96,
4872 if (err < 0)
4877 if (err < 0)
4881 return 0;
4897 jack->block_report = 0;
4918 return 0;
4920 /* if CrystalVoice if off, vipsource should be 0 */
4922 (val == 0)) {
4923 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4930 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4932 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4940 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4942 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4956 return 0;
4960 chipio_set_stream_control(codec, 0x03, 0);
4961 chipio_set_stream_control(codec, 0x04, 0);
4963 /* if CrystalVoice is off, vipsource should be 0 */
4965 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4967 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4970 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4975 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4987 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4994 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5000 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5003 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5009 chipio_set_stream_control(codec, 0x03, 1);
5010 chipio_set_stream_control(codec, 0x04, 1);
5048 ca0132_mic_boost_set(codec, 0);
5056 ca0132_set_dmic(codec, 0);
5059 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5062 return 0;
5080 chipio_set_stream_control(codec, 0x03, 0);
5081 chipio_set_stream_control(codec, 0x04, 0);
5090 ca0113_mmio_gpio_set(codec, 0, false);
5101 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5105 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5111 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5121 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5123 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5125 chipio_set_stream_control(codec, 0x03, 1);
5126 chipio_set_stream_control(codec, 0x04, 1);
5129 chipio_write(codec, 0x18B098, 0x0000000C);
5130 chipio_write(codec, 0x18B09C, 0x0000000C);
5133 chipio_write(codec, 0x18B098, 0x0000000C);
5134 chipio_write(codec, 0x18B09C, 0x000000CC);
5137 chipio_write(codec, 0x18B098, 0x0000000C);
5138 chipio_write(codec, 0x18B09C, 0x0000004C);
5146 ca0132_mic_boost_set(codec, 0);
5150 ca0113_mmio_gpio_set(codec, 0, false);
5156 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5159 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5164 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5173 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5179 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5184 chipio_write(codec, 0x18B098, 0x00000000);
5185 chipio_write(codec, 0x18B09C, 0x00000000);
5190 chipio_set_stream_control(codec, 0x03, 1);
5191 chipio_set_stream_control(codec, 0x04, 1);
5197 ca0113_mmio_gpio_set(codec, 0, true);
5206 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5217 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5219 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5221 chipio_set_stream_control(codec, 0x03, 1);
5222 chipio_set_stream_control(codec, 0x04, 1);
5226 chipio_write(codec, 0x18B098, 0x0000000C);
5227 chipio_write(codec, 0x18B09C, 0x000000CC);
5230 chipio_write(codec, 0x18B098, 0x0000000C);
5231 chipio_write(codec, 0x18B09C, 0x0000004C);
5241 return 0;
5273 * They return 0 if no changed. Return 1 if changed.
5289 ca0132_voicefx.reqs[0], tmp);
5302 int err = 0;
5305 if ((idx < 0) || (idx >= num_fx))
5306 return 0; /* no changed */
5312 val = 0;
5317 val = 0;
5325 val = 0;
5329 val = 0;
5344 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5349 * to module ID 0x47. No clue why.
5363 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5369 val = 0;
5372 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5375 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5377 ca0132_effects[idx].reqs[0], on);
5379 if (err < 0)
5380 return 0; /* no changed */
5392 int i, ret = 0;
5413 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5414 AC_VERB_GET_CONV, 0);
5415 if (oldval != 0)
5416 snd_hda_codec_write(codec, spec->adcs[0], 0,
5418 0);
5427 if (oldval != 0)
5428 snd_hda_codec_write(codec, spec->adcs[0], 0,
5440 int i, ret = 0;
5453 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5468 int ret = 0;
5471 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5472 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5474 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5475 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5483 int ret = 0;
5485 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5486 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5494 for (i = 0; i < 4; i++)
5495 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5497 return 0;
5508 return 0;
5516 hda_nid_t shared_nid = 0;
5518 int ret = 0;
5565 0, dir);
5579 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5595 int i = 0;
5608 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5612 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5617 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5621 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5626 return 0;
5642 return 0;
5655 return 0;
5671 return 0;
5681 uinfo->value.integer.min = 0;
5685 return 0;
5705 return 0;
5715 return 0;
5730 return 0;
5737 return 0;
5744 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5762 return 0;
5771 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5772 return 0;
5780 int sel = ucontrol->value.enumerated.item[0];
5784 return 0;
5816 return 0;
5825 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5826 return 0;
5834 int sel = ucontrol->value.enumerated.item[0];
5838 return 0;
5869 return 0;
5878 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5879 return 0;
5887 int sel = ucontrol->value.enumerated.item[0];
5891 return 0;
5898 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5919 return 0;
5928 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5929 return 0;
5937 int sel = ucontrol->value.enumerated.item[0];
5948 return 0;
5971 return 0;
5980 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5981 return 0;
5989 int sel = ucontrol->value.enumerated.item[0];
5994 return 0;
6022 return 0;
6031 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6032 return 0;
6040 int sel = ucontrol->value.enumerated.item[0];
6044 return 0;
6075 return 0;
6084 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6085 return 0;
6093 int sel = ucontrol->value.enumerated.item[0];
6099 return 0;
6107 case 0:
6139 return 0;
6148 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6149 return 0;
6157 int i, err = 0;
6158 int sel = ucontrol->value.enumerated.item[0];
6162 return 0;
6167 * Idx 0 is default.
6170 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6174 if (err < 0)
6178 if (err >= 0)
6196 return 0;
6205 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6206 return 0;
6214 int i, err = 0;
6215 int sel = ucontrol->value.enumerated.item[0];
6218 return 0;
6224 * Idx 0 is default.
6227 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6231 if (err < 0)
6235 if (err >= 0) {
6238 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6263 return 0;
6269 return 0;
6273 if (nid == spec->input_pins[0]) {
6275 return 0;
6280 return 0;
6285 return 0;
6290 return 0;
6293 return 0;
6305 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6342 if (nid == spec->input_pins[0]) {
6361 return 0;
6369 return 0;
6377 return 0;
6406 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6438 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6448 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6477 return 0;
6488 hda_nid_t shared_nid = 0;
6512 0, dir);
6533 hda_nid_t vnid = 0;
6536 case 0x02:
6539 case 0x07:
6577 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6587 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6605 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6622 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6657 VOICEFX, 1, 0, HDA_INPUT);
6669 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6686 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6703 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6720 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6763 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6795 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6804 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6811 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6829 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6846 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6874 * I think this has to do with the pin for rear surround being 0x11,
6875 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6893 int err = 0;
6906 elem, hinfo->channels_max, 0, &chmap);
6907 if (err < 0)
6922 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6923 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6924 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6925 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6927 0x12, 1, HDA_INPUT),
6945 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6947 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6948 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6949 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6950 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6951 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6952 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6953 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6955 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6956 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6967 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6969 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6970 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6971 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6972 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6973 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6974 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6977 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6978 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6988 int err = 0;
6991 for (i = 0; i < spec->num_mixers; i++) {
6993 if (err < 0)
6998 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7002 "Playback Volume", 0);
7006 true, 0, &spec->vmaster_mute.sw_kctl);
7007 if (err < 0)
7015 for (i = 0; i < num_fx; i++) {
7026 if (err < 0)
7036 if (err < 0)
7040 if (err < 0)
7044 "Enable OutFX", 0);
7045 if (err < 0)
7050 if (err < 0)
7054 for (i = 0; i < num_sliders; i++) {
7059 if (err < 0)
7066 if (err < 0)
7070 "PlayEnhancement", 0);
7071 if (err < 0)
7076 if (err < 0)
7080 if (err < 0)
7090 if (err < 0)
7093 if (err < 0)
7096 if (err < 0)
7099 if (err < 0)
7102 if (err < 0)
7105 if (err < 0)
7108 if (err < 0)
7116 if (err < 0)
7125 if (err < 0)
7128 if (err < 0)
7133 if (err < 0)
7145 if (err < 0)
7151 if (err < 0)
7154 if (err < 0)
7161 if (err < 0)
7168 return 0;
7174 int err = 0;
7179 if (err < 0)
7185 if (err < 0)
7189 return 0;
7249 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7254 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7275 return 0;
7292 return 0;
7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7309 return 0;
7326 return 0;
7334 snd_hda_codec_write(codec, pin, 0,
7339 snd_hda_codec_write(codec, dac, 0,
7348 snd_hda_codec_write(codec, pin, 0,
7350 AMP_IN_UNMUTE(0));
7353 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7354 AMP_IN_UNMUTE(0));
7356 /* init to 0 dB and unmute. */
7357 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7358 HDA_AMP_VOLMASK, 0x5a);
7359 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7360 HDA_AMP_MUTE, 0);
7386 ca0132_set_vipsource(codec, 0);
7390 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7393 val |= 0x80;
7394 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7397 if (!(spec->dmic_ctl & 0x20))
7402 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7406 val &= 0x5f;
7407 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7410 if (!(spec->dmic_ctl & 0x20))
7411 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7430 * Bit 2-0: MPIO select
7434 val = 0x01;
7435 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7439 * Bit 2-0: Data1 MPIO select
7444 val = 0x83;
7445 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7448 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7449 * Bit 3-0: Channel mask
7456 val = 0x33;
7458 val = 0x23;
7461 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7474 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7475 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7486 for (i = 0; i < spec->multiout.num_dacs; i++)
7489 for (i = 0; i < spec->num_outputs; i++)
7492 for (i = 0; i < spec->num_inputs; i++) {
7507 if (status >= 0) {
7508 /* AND against 0xfff to get the active channel bits. */
7509 tmp = tmp & 0xfff;
7524 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7527 if (status < 0)
7552 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7553 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7557 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7566 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7571 dsp_dma_stream_ids[i], 0);
7585 /* Make sure stream 0x0c is six channels. */
7586 chipio_set_stream_channels(codec, 0x0c, 6);
7588 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7598 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7601 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7604 * 0x0001f8c0
7608 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7609 * entry within the 0x190000 range, and when a range of entries is in use, the
7610 * ending value is overwritten with 0xff.
7611 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7612 * streamID's, where each entry is a starting 0x190000 port offset.
7613 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7621 * 0x00-0x1f: HDA audio stream input/output ports.
7622 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7623 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7624 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7625 * 0xe0-0xff: DAC/ADC audio input/output ports.
7628 * 0x03: Mic1 ADC to DSP.
7629 * 0x04: Mic2 ADC to DSP.
7630 * 0x05: HDA node 0x02 audio stream to DSP.
7631 * 0x0f: DSP Mic exit to HDA node 0x07.
7632 * 0x0c: DSP processed audio to DACs.
7633 * 0x14: DAC0, front L/R.
7647 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7651 * Check if the stream's port value is 0xff, because the 8051 may not
7655 if (stream_offset == 0xff) {
7656 for (i = 0; i < 5; i++) {
7659 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7662 if (stream_offset != 0xff)
7667 if (stream_offset == 0xff) {
7668 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7674 stream_offset *= 0x04;
7675 stream_offset += 0x190000;
7677 for (i = 0; i < remap_data->count; i++) {
7684 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7692 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7697 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7702 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7731 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7736 dspio_set_uint_param(codec, 0x96, i, tmp);
7741 dspio_set_uint_param(codec, 0x96, i, tmp);
7744 for (i = 0; i < 6; i++)
7745 dspio_set_uint_param(codec, 0x96,
7761 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7765 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7771 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7773 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7777 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7778 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7790 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7791 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7793 /* Setup stream 0x14 with it's source and destination points */
7794 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7795 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7796 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7797 chipio_set_stream_channels(codec, 0x14, 2);
7798 chipio_set_stream_control(codec, 0x14, 1);
7818 chipio_remap_stream(codec, &stream_remap_data[0]);
7846 chipio_set_stream_control(codec, 0x03, 0);
7847 chipio_set_stream_control(codec, 0x04, 0);
7853 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7855 chipio_set_stream_control(codec, 0x03, 1);
7856 chipio_set_stream_control(codec, 0x04, 1);
7860 chipio_write(codec, 0x18b098, 0x0000000c);
7861 chipio_write(codec, 0x18b09C, 0x0000000c);
7864 chipio_write(codec, 0x18b098, 0x0000000c);
7865 chipio_write(codec, 0x18b09c, 0x0000004c);
7876 chipio_8051_write_direct(codec, 0x93, 0x10);
7877 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7879 writeb(0xff, spec->mem_base + 0x304);
7880 writeb(0xff, spec->mem_base + 0x304);
7881 writeb(0xff, spec->mem_base + 0x304);
7882 writeb(0xff, spec->mem_base + 0x304);
7883 writeb(0x00, spec->mem_base + 0x100);
7884 writeb(0xff, spec->mem_base + 0x304);
7885 writeb(0x00, spec->mem_base + 0x100);
7886 writeb(0xff, spec->mem_base + 0x304);
7887 writeb(0x00, spec->mem_base + 0x100);
7888 writeb(0xff, spec->mem_base + 0x304);
7889 writeb(0x00, spec->mem_base + 0x100);
7890 writeb(0xff, spec->mem_base + 0x304);
7892 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7893 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7894 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7904 chipio_set_control_param(codec, 3, 0);
7911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7912 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7914 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7919 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7920 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7921 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7922 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7923 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7934 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7936 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7938 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7939 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7940 chipio_set_stream_channels(codec, 0x18, 6);
7941 chipio_set_stream_control(codec, 0x18, 1);
7945 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7947 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7956 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7957 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7958 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7959 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7961 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7963 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7964 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7965 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7966 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7967 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7968 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7969 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7970 ca0113_mmio_gpio_set(codec, 0, true);
7972 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7974 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7976 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7977 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7989 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7990 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7991 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7992 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7993 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7994 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7995 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7996 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8005 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8006 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8008 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8010 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8011 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8013 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8014 chipio_set_stream_channels(codec, 0x18, 6);
8015 chipio_set_stream_control(codec, 0x18, 1);
8023 0x41, 0x45, 0x40, 0x43, 0x51
8026 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8030 for (i = 0; i < ARRAY_SIZE(addr); i++)
8038 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8041 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8047 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8049 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8050 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8051 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8052 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8057 for (i = 0; i < ARRAY_SIZE(target); i++)
8058 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8060 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8061 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8062 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8064 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8065 chipio_set_stream_channels(codec, 0x21, 2);
8066 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8068 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8074 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8076 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8080 * seemingly sends data to the HDA node 0x09, which is the digital
8087 ca0113_mmio_gpio_set(codec, 0, 1);
8090 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8091 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8092 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8093 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8095 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8096 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8098 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8099 chipio_set_stream_channels(codec, 0x18, 6);
8116 chipio_8051_write_direct(codec, 0x93, 0x10);
8118 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8120 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8121 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8127 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8128 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8130 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8135 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8155 for (idx = 0; idx < num_fx; idx++) {
8156 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8165 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8168 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8172 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8173 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8177 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8181 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8203 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8207 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8211 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8224 for (idx = 0; idx < num_fx; idx++) {
8225 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8258 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8259 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8263 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8267 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8271 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8277 for (idx = 0; idx < num_fx; idx++) {
8278 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8307 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8308 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8309 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8310 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8312 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8313 ca0113_mmio_gpio_set(codec, 0, false);
8314 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8318 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8319 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8323 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8327 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8331 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8342 for (idx = 0; idx < num_fx; idx++) {
8343 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8372 dspio_set_uint_param(codec, 0x96,
8374 dspio_set_uint_param(codec, 0x96,
8377 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8380 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8381 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8383 ca0113_mmio_gpio_set(codec, 0, false);
8387 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8388 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8392 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8396 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8400 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8401 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8412 * Not sure why, but these are both set to 1. They're only set to 0
8415 ca0113_mmio_gpio_set(codec, 0, true);
8419 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8420 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8421 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8425 for (idx = 0; idx < num_fx; idx++) {
8426 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8450 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8451 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8453 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8457 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8459 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8461 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8463 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8465 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8479 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8480 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8481 chipio_set_control_param(codec, 0, 0);
8482 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8519 codec->card->dev) != 0)
8526 codec->card->dev) != 0)
8541 codec->card->dev) != 0)
8546 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8593 if (dspio_get_response_data(codec) >= 0)
8594 spec->wait_scp = 0;
8645 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8652 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8654 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8662 {0x15, 0x70D, 0xF0},
8663 {0x15, 0x70E, 0xFE},
8664 {0x15, 0x707, 0x75},
8665 {0x15, 0x707, 0xD3},
8666 {0x15, 0x707, 0x09},
8667 {0x15, 0x707, 0x53},
8668 {0x15, 0x707, 0xD4},
8669 {0x15, 0x707, 0xEF},
8670 {0x15, 0x707, 0x75},
8671 {0x15, 0x707, 0xD3},
8672 {0x15, 0x707, 0x09},
8673 {0x15, 0x707, 0x02},
8674 {0x15, 0x707, 0x37},
8675 {0x15, 0x707, 0x78},
8676 {0x15, 0x53C, 0xCE},
8677 {0x15, 0x575, 0xC9},
8678 {0x15, 0x53D, 0xCE},
8679 {0x15, 0x5B7, 0xC9},
8680 {0x15, 0x70D, 0xE8},
8681 {0x15, 0x70E, 0xFE},
8682 {0x15, 0x707, 0x02},
8683 {0x15, 0x707, 0x68},
8684 {0x15, 0x707, 0x62},
8685 {0x15, 0x53A, 0xCE},
8686 {0x15, 0x546, 0xC9},
8687 {0x15, 0x53B, 0xCE},
8688 {0x15, 0x5E8, 0xC9},
8694 {0x15, 0x70D, 0x20},
8695 {0x15, 0x70E, 0x19},
8696 {0x15, 0x707, 0x00},
8697 {0x15, 0x539, 0xCE},
8698 {0x15, 0x546, 0xC9},
8699 {0x15, 0x70D, 0xB7},
8700 {0x15, 0x70E, 0x09},
8701 {0x15, 0x707, 0x10},
8702 {0x15, 0x70D, 0xAF},
8703 {0x15, 0x70E, 0x09},
8704 {0x15, 0x707, 0x01},
8705 {0x15, 0x707, 0x05},
8706 {0x15, 0x70D, 0x73},
8707 {0x15, 0x70E, 0x09},
8708 {0x15, 0x707, 0x14},
8709 {0x15, 0x6FF, 0xC4},
8729 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8730 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8732 snd_hda_codec_write(codec, codec->core.afg, 0,
8733 AC_VERB_SET_CODEC_RESET, 0);
8734 snd_hda_codec_write(codec, codec->core.afg, 0,
8735 AC_VERB_SET_CODEC_RESET, 0);
8744 spec->cur_mic_boost = 0;
8746 for (i = 0; i < VNODES_COUNT; i++) {
8747 spec->vnode_lvol[i] = 0x5a;
8748 spec->vnode_rvol[i] = 0x5a;
8749 spec->vnode_lswitch[i] = 0;
8750 spec->vnode_rswitch[i] = 0;
8757 for (i = 0; i < num_fx; i++) {
8758 on = (unsigned int)ca0132_effects[i].reqs[0];
8759 spec->effects_switch[i] = on ? 1 : 0;
8767 spec->speaker_range_val[0] = 1;
8771 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8777 spec->voicefx_val = 0;
8779 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8800 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8811 for (i = 0; i < 4; i++)
8812 writeb(0x0, spec->mem_base + 0x100);
8813 for (i = 0; i < 8; i++)
8814 writeb(0xb3, spec->mem_base + 0x304);
8816 ca0113_mmio_gpio_set(codec, 0, false);
8825 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8828 snd_hda_codec_write(codec, 0x11, 0,
8829 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8831 for (i = 0; i < ARRAY_SIZE(pins); i++)
8832 snd_hda_codec_write(codec, pins[i], 0,
8833 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8838 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8841 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8842 snd_hda_codec_write(codec, pins[i], 0,
8843 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8851 if (dir >= 0)
8852 snd_hda_codec_write(codec, 0x01, 0,
8854 if (mask >= 0)
8855 snd_hda_codec_write(codec, 0x01, 0,
8858 if (data >= 0)
8859 snd_hda_codec_write(codec, 0x01, 0,
8865 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8868 for (i = 0; i < ARRAY_SIZE(pins); i++)
8869 snd_hda_codec_write(codec, pins[i], 0,
8870 AC_VERB_SET_POWER_STATE, 0x03);
8875 chipio_set_stream_control(codec, 0x03, 0);
8876 chipio_set_stream_control(codec, 0x04, 0);
8879 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8880 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8881 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8883 chipio_set_stream_control(codec, 0x14, 0);
8884 chipio_set_stream_control(codec, 0x0C, 0);
8886 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8887 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8889 chipio_write(codec, 0x18a020, 0x00000083);
8891 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8892 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8893 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8895 chipio_set_stream_control(codec, 0x0C, 0);
8897 chipio_set_control_param(codec, 0x0D, 0x24);
8902 snd_hda_codec_write(codec, 0x0B, 0,
8903 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8911 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8912 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8917 chipio_set_stream_control(codec, 0x03, 0);
8918 chipio_set_stream_control(codec, 0x04, 0);
8920 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8921 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8922 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8923 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8924 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8925 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8926 ca0113_mmio_gpio_set(codec, 0, false);
8929 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8930 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8932 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8934 chipio_set_stream_control(codec, 0x18, 0);
8935 chipio_set_stream_control(codec, 0x0c, 0);
8937 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8942 chipio_set_stream_control(codec, 0x18, 0);
8943 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8944 chipio_set_stream_channels(codec, 0x21, 0);
8945 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8946 chipio_set_control_param(codec, 0x20, 0x01);
8948 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8950 chipio_set_stream_control(codec, 0x18, 0);
8951 chipio_set_stream_control(codec, 0x0c, 0);
8953 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8954 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8955 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8956 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8957 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8958 ca0113_mmio_gpio_set(codec, 0, false);
8960 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8962 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8963 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8968 chipio_set_stream_control(codec, 0x03, 0);
8969 chipio_set_stream_control(codec, 0x04, 0);
8970 chipio_set_stream_control(codec, 0x14, 0);
8971 chipio_set_stream_control(codec, 0x0C, 0);
8973 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8974 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8976 chipio_write(codec, 0x18a020, 0x00000083);
8978 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8979 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8983 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8988 ca0113_mmio_gpio_set(codec, 0, false);
8990 ca0113_mmio_gpio_set(codec, 0, true);
9016 unsigned int cur_address = 0x390;
9018 unsigned int failure = 0;
9026 for (i = 0; i < 4; i++) {
9028 cur_address += 0x4;
9030 for (i = 0; i < 4; i++) {
9031 if (dsp_data_check[i] == 0xa1a2a3a4)
9043 while (failure && (reload != 0)) {
9048 failure = 0;
9049 for (i = 0; i < 4; i++) {
9051 cur_address += 0x4;
9053 for (i = 0; i < 4; i++) {
9054 if (dsp_data_check[i] == 0xa1a2a3a4)
9070 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9075 * to 0 just incase a value has lingered from a boot into Windows.
9079 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9080 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9081 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9082 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9083 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9084 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9085 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9086 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9096 writel(0x00820680, spec->mem_base + 0x01C);
9097 writel(0x00820680, spec->mem_base + 0x01C);
9099 chipio_write(codec, 0x18b0a4, 0x000000c2);
9101 snd_hda_codec_write(codec, 0x11, 0,
9102 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9107 chipio_write(codec, 0x18b0a4, 0x000000c2);
9109 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9111 snd_hda_codec_write(codec, 0x11, 0,
9112 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9117 chipio_write(codec, 0x18b0a4, 0x000000c2);
9119 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9120 chipio_8051_write_exram(codec, 0x1920, 0x00);
9121 chipio_8051_write_exram(codec, 0x1921, 0x40);
9123 snd_hda_codec_write(codec, 0x11, 0,
9124 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9134 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9135 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9138 chipio_write(codec, 0x189000, 0x0001f100);
9140 chipio_write(codec, 0x18900c, 0x0001f100);
9145 * 0xfa92 in exram. This function seems to have something to do with
9149 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9151 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9156 chipio_write(codec, 0x18902c, 0x00000000);
9158 chipio_write(codec, 0x18902c, 0x00000003);
9161 for (i = 0; i < ARRAY_SIZE(addr); i++)
9171 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9172 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9176 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9177 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9178 0x000000c1, 0x00000080
9182 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9183 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9184 0x000000c1, 0x00000080
9188 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9189 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9190 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9191 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9195 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9196 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9197 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9198 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9199 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9200 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9201 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9202 0x00000080, 0x00880680
9212 for (i = 0; i < 3; i++)
9213 writel(0x00000000, spec->mem_base + addr[i]);
9218 tmp[0] = 0x00880480;
9219 tmp[1] = 0x00000080;
9222 tmp[0] = 0x00820680;
9223 tmp[1] = 0x00000083;
9226 tmp[0] = 0x00880680;
9227 tmp[1] = 0x00000083;
9230 tmp[0] = 0x00000000;
9231 tmp[1] = 0x00000000;
9235 for (i = 0; i < 2; i++)
9251 for (i = 0; i < count; i++)
9266 writel(0x00000680, spec->mem_base + 0x1c);
9267 writel(0x00880680, spec->mem_base + 0x1c);
9270 for (i = 0; i < count; i++) {
9273 * a different value to 0x20c.
9276 writel(0x00800001, spec->mem_base + addr[i]);
9284 writel(0x00880680, spec->mem_base + 0x1c);
9306 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9307 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9311 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9312 0x01, 0x6b, 0x57
9317 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9330 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9332 chipio_8051_write_direct(codec, 0x93, 0x10);
9333 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9336 tmp[0] = 0x03;
9337 tmp[1] = 0x03;
9338 tmp[2] = 0x07;
9340 tmp[0] = 0x0f;
9341 tmp[1] = 0x0f;
9342 tmp[2] = 0x0f;
9345 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9352 for (i = 0; cur_addr < 12; i++, cur_addr++)
9358 writel(0x00800001, spec->mem_base + 0x20c);
9361 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9362 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9364 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9367 chipio_8051_write_direct(codec, 0x90, 0x00);
9368 chipio_8051_write_direct(codec, 0x90, 0x10);
9371 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9409 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9410 chipio_write(codec, 0x18b030, 0x00000020);
9413 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9417 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9420 chipio_write(codec, 0x18b008, 0x000000f8);
9421 chipio_write(codec, 0x18b008, 0x000000f0);
9422 chipio_write(codec, 0x18b030, 0x00000020);
9423 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9426 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9461 return 0;
9511 for (i = 0; i < spec->num_outputs; i++)
9512 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9514 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9516 for (i = 0; i < spec->num_inputs; i++)
9523 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9524 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9525 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9526 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9552 return 0;
9561 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9564 for (i = 0; i < spec->num_inputs; i++)
9567 return 0;
9625 spec->dacs[0] = 0x2;
9626 spec->dacs[1] = 0x3;
9627 spec->dacs[2] = 0x4;
9673 spec->out_pins[0] = 0x0b; /* speaker out */
9674 spec->out_pins[1] = 0x0f;
9675 spec->shared_out_nid = 0x2;
9676 spec->unsol_tag_hp = 0x0f;
9678 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9679 spec->adcs[1] = 0x8; /* analog mic2 */
9680 spec->adcs[2] = 0xa; /* what u hear */
9683 spec->input_pins[0] = 0x12;
9684 spec->input_pins[1] = 0x11;
9685 spec->input_pins[2] = 0x13;
9686 spec->shared_mic_nid = 0x7;
9687 spec->unsol_tag_amic1 = 0x11;
9692 spec->out_pins[0] = 0x0B; /* Line out */
9693 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9694 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9695 spec->out_pins[3] = 0x11; /* Rear surround */
9696 spec->shared_out_nid = 0x2;
9700 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9701 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9702 spec->adcs[2] = 0xa; /* what u hear */
9705 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9706 spec->input_pins[1] = 0x13; /* What U Hear */
9707 spec->shared_mic_nid = 0x7;
9708 spec->unsol_tag_amic1 = spec->input_pins[0];
9711 spec->dig_out = 0x05;
9713 spec->dig_in = 0x09;
9717 spec->out_pins[0] = 0x0B; /* Line out */
9718 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9719 spec->out_pins[2] = 0x10; /* Center/LFE */
9720 spec->out_pins[3] = 0x11; /* Rear surround */
9721 spec->shared_out_nid = 0x2;
9725 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9726 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9727 spec->adcs[2] = 0xa; /* what u hear */
9730 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9731 spec->input_pins[1] = 0x13; /* What U Hear */
9732 spec->shared_mic_nid = 0x7;
9733 spec->unsol_tag_amic1 = spec->input_pins[0];
9736 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9739 spec->input_pins[0] = 0x11; /* RCA Line-in */
9741 spec->dig_out = 0x05;
9744 spec->dig_in = 0x09;
9749 spec->out_pins[0] = 0x0B; /* Line out */
9750 spec->out_pins[1] = 0x11; /* Rear headphone out */
9751 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9752 spec->out_pins[3] = 0x0F; /* Rear surround */
9753 spec->shared_out_nid = 0x2;
9757 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9758 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9759 spec->adcs[2] = 0xa; /* what u hear */
9762 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9763 spec->input_pins[1] = 0x13; /* What U Hear */
9764 spec->shared_mic_nid = 0x7;
9765 spec->unsol_tag_amic1 = spec->input_pins[0];
9768 spec->dig_out = 0x05;
9773 spec->out_pins[0] = 0x0B; /* Line out */
9774 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9775 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9776 spec->out_pins[3] = 0x11; /* Rear surround */
9777 spec->shared_out_nid = 0x2;
9781 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9782 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9783 spec->adcs[2] = 0x0a; /* what u hear */
9786 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9787 spec->input_pins[1] = 0x13; /* What U Hear */
9788 spec->shared_mic_nid = 0x7;
9789 spec->unsol_tag_amic1 = spec->input_pins[0];
9792 spec->dig_out = 0x05;
9797 spec->out_pins[0] = 0x0b; /* speaker out */
9798 spec->out_pins[1] = 0x10; /* headphone out */
9799 spec->shared_out_nid = 0x2;
9802 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9803 spec->adcs[1] = 0x8; /* analog mic2 */
9804 spec->adcs[2] = 0xa; /* what u hear */
9807 spec->input_pins[0] = 0x12;
9808 spec->input_pins[1] = 0x11;
9809 spec->input_pins[2] = 0x13;
9810 spec->shared_mic_nid = 0x7;
9811 spec->unsol_tag_amic1 = spec->input_pins[0];
9814 spec->dig_out = 0x05;
9816 spec->dig_in = 0x09;
9841 spec->spec_init_verbs[0].nid = 0x0b;
9842 spec->spec_init_verbs[0].param = 0x78D;
9843 spec->spec_init_verbs[0].verb = 0x00;
9847 spec->spec_init_verbs[2].nid = 0x0b;
9849 spec->spec_init_verbs[2].verb = 0x02;
9851 spec->spec_init_verbs[3].nid = 0x10;
9852 spec->spec_init_verbs[3].param = 0x78D;
9853 spec->spec_init_verbs[3].verb = 0x02;
9855 spec->spec_init_verbs[4].nid = 0x10;
9857 spec->spec_init_verbs[4].verb = 0x02;
9861 return 0;
9873 case 0x11020033:
9876 case 0x1102003f:
9924 spec->mixers[0] = desktop_mixer;
9928 spec->mixers[0] = desktop_mixer;
9934 spec->mixers[0] = desktop_mixer;
9938 spec->mixers[0] = r3di_mixer;
9942 spec->mixers[0] = desktop_mixer;
9946 spec->mixers[0] = desktop_mixer;
9950 spec->mixers[0] = ca0132_mixer;
9979 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9997 if (err < 0)
10001 if (err < 0)
10006 return 0;
10048 return 0;
10065 HDA_CODEC_ID(0x11020011, "CA0132"),