Lines Matching +full:0 +full:x2e00
29 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
33 #define TAG_NO_CIP_HEADER 0
40 #define CIP_EOH_MASK 0x80000000
42 #define CIP_SID_MASK 0x3f000000
43 #define CIP_DBS_MASK 0x00ff0000
45 #define CIP_SPH_MASK 0x00000400
47 #define CIP_DBC_MASK 0x000000ff
49 #define CIP_FMT_MASK 0x3f000000
50 #define CIP_FDF_MASK 0x00ff0000
52 #define CIP_FDF_NO_DATA 0xff
53 #define CIP_SYT_MASK 0x0000ffff
54 #define CIP_SYT_NO_INFO 0xffff
61 #define CIP_FMT_AM 0x10
62 #define AMDTP_FDF_NO_DATA 0xff
70 #define HEADER_TSTAMP_MASK 0x0000ffff
73 #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing.
111 s->packet_index = 0;
118 return 0;
166 struct snd_interval t = {0};
167 unsigned int step = 0;
170 for (i = 0; i < CIP_SFC_COUNT; ++i) {
175 if (step == 0)
245 if (err < 0)
258 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
262 if (err < 0)
264 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
268 if (err < 0)
291 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
311 return 0;
342 cip_header_size = 0;
357 s->pcm_buffer_pointer = 0;
358 s->pcm_period_pointer = 0;
371 for (i = 0; i < count; ++i) {
377 desc->data_blocks = 0;
391 for (i = 0; i < count; ++i) {
410 desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40));
413 desc->data_blocks = 11 * (sfc >> 1) + (phase == 0);
415 phase = 0;
451 phase = 0;
472 for (i = 0; i < count; ++i) {
487 unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f;
488 unsigned int syt_cycle_lo = (syt & 0xf000) >> 12;
498 syt_offset = syt_cycle_lo * TICKS_PER_CYCLE + (syt & 0x0fff);
530 for (i = 0; i < desc_count; ++i) {
566 for (i = 0; i < count; ++i) {
659 params->sy = 0;
663 if (err < 0) {
669 s->packet_index = 0;
678 !!(params->header_length == 0 && params->payload_length == 0);
695 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
717 if (header_length > 0) {
741 cip_header[0] = be32_to_cpu(buf[0]);
748 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
753 cip_header[0], cip_header[1]);
758 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
763 cip_header[0], cip_header[1]);
769 if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
770 *data_blocks = 0;
773 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
775 if (data_block_quadlets == 0) {
778 cip_header[0]);
788 dbc = cip_header[0] & CIP_DBC_MASK;
789 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
793 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
802 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
810 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
825 return 0;
839 payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
844 cip_header_size = 0;
853 if (cip_header_size > 0) {
860 if (err < 0)
865 *data_blocks = 0;
866 *syt = 0;
871 *syt = 0;
874 *data_block_counter = 0;
880 return 0;
888 return (((tstamp >> 13) & 0x07) * CYCLES_PER_SECOND) + (tstamp & 0x1fff);
916 return 0;
942 u32 curr_cycle_time = 0;
949 *desc_count = 0;
950 for (i = 0; i < packet_count; ++i) {
970 desc->syt = 0;
971 desc->data_blocks = 0;
983 lost = (compare_ohci_cycle_count(safe_cycle, cycle) < 0);
994 if (err < 0)
1004 dbc = (dbc + desc->data_blocks) & 0xff;
1016 return 0;
1042 for (i = 0; i < packet_count; ++i) {
1056 dbc = (dbc + desc->data_blocks) & 0xff;
1061 dbc = (dbc + desc->data_blocks) & 0xff;
1093 unsigned int data_block_count = 0;
1100 if (count == 0)
1104 for (i = 0; i < count - 1; ++i)
1109 if (err < 0)
1114 curr_cycle = compute_ohci_iso_ctx_cycle_count((cycle_time >> 12) & 0x0000ffff);
1119 if (compare_ohci_cycle_count(latest_cycle, curr_cycle) > 0)
1124 // value expectedly corresponds to a few packets (0-2) since the packet arrived at
1126 for (i = 0; i < cycle_gap; ++i) {
1133 if (compare_ohci_cycle_count(latest_cycle, curr_cycle) < 0)
1138 for (i = 0; i < cycle_gap; ++i) {
1158 unsigned int data_block_count = 0;
1162 for (i = 0; i < count; ++i) {
1186 if (s->packet_index < 0)
1199 pkt_header_length = 0;
1214 for (i = 0; i < packets; ++i) {
1230 if (queue_out_packet(s, template, sched_irq) < 0) {
1252 if (s->packet_index < 0)
1260 for (i = 0; i < packets; ++i) {
1262 .header_length = 0,
1263 .payload_length = 0,
1267 if (queue_out_packet(s, ¶ms, sched_irq) < 0) {
1287 if (s->packet_index < 0)
1292 offset = 0;
1296 if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0)
1302 if (offset > 0) {
1318 s->ctx_data.rx.cache_pos = 0;
1342 if (s->packet_index < 0)
1348 desc_count = 0;
1350 if (err < 0) {
1363 for (i = 0; i < desc_count; ++i)
1368 for (i = 0; i < packet_count; ++i) {
1369 struct fw_iso_packet params = {0};
1371 if (queue_in_packet(s, ¶ms) < 0) {
1387 if (s->packet_index < 0)
1396 for (i = 0; i < packets; ++i) {
1397 struct fw_iso_packet params = {0};
1399 if (queue_in_packet(s, ¶ms) < 0) {
1415 if (s->packet_index < 0)
1420 offset = 0;
1425 if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0)
1434 if (offset > 0) {
1467 if (s->packet_index < 0)
1473 events = 0;
1475 for (i = 0; i < count; ++i) {
1486 data_blocks = 0;
1498 data_blocks = 0;
1512 if (events > 0)
1517 unsigned int stream_count = 0;
1518 unsigned int event_starts_count = 0;
1539 compare_ohci_cycle_count(next_cycle, cycle) > 0)
1604 unsigned int rx_count = 0;
1605 unsigned int rx_ready_count = 0;
1617 cached_cycles = calculate_cached_cycle_count(tx, 0);
1635 if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0)
1704 s->data_block_counter = 0;
1718 ctx_header_size = 0; // No effect for IT context.
1723 if (err < 0)
1750 s->ctx_data.tx.cache.pos = 0;
1767 [CIP_SFC_44100] = { 0, 67 },
1768 [CIP_SFC_88200] = { 0, 67 },
1769 [CIP_SFC_176400] = { 0, 67 },
1778 s->ctx_data.rx.seq.pos = 0;
1785 s->ctx_data.rx.event_count = 0;
1805 for (i = 0; i < s->queue_size; ++i) {
1812 s->packet_index = 0;
1821 params.header_length = 0;
1822 params.payload_length = 0;
1831 if (err < 0)
1833 } while (s->packet_index > 0);
1841 err = fw_iso_context_start(s->context, -1, 0, tag);
1842 if (err < 0)
1845 return 0;
1904 return 0;
1975 d->events_per_period = 0;
1977 return 0;
2015 return 0;
2023 unsigned int dst_index = 0;
2029 unsigned int src_index = 0;
2062 return 0;
2087 if (err < 0)
2109 if (events_per_period == 0)
2111 if (events_per_buffer == 0)
2118 unsigned int idle_irq_interval = 0;
2127 if (err < 0)
2131 return 0;
2157 d->events_per_period = 0;