Lines Matching +full:tx +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
19 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
20 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
49 * TX/RX fifo control register (CR). P48
74 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
75 #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
76 #define SR_TXU (1 << 9) /* tx underrun */
77 #define SR_RXO (1 << 8) /* rx overrun */
78 #define SR_TXB (1 << 7) /* tx busy */
79 #define SR_RXB (1 << 6) /* rx busy */
80 #define SR_TXFF (1 << 5) /* tx fifo full */
81 #define SR_RXFF (1 << 4) /* rx fifo full */
82 #define SR_TXHE (1 << 3) /* tx fifo half empty */
83 #define SR_RXHF (1 << 2) /* rx fifo half full */
84 #define SR_TXFE (1 << 1) /* tx fifo empty */
85 #define SR_RXFE (1 << 0) /* rx fifo empty */
90 #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */
91 #define ISR_URINTR (1 << 5) /* tx underflow */
92 #define ISR_ORINTR (1 << 4) /* rx overflow */
93 #define ISR_RXINTR (1 << 3) /* rx fifo */
94 #define ISR_TXINTR (1 << 2) /* tx fifo intr */
95 #define ISR_RXTOINTR (1 << 1) /* tx timeout */
96 #define ISR_TXCINTR (1 << 0) /* tx complete */
112 #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
113 #define ISR_UR (1 << 5) /* tx fifo underrun */
114 #define ISR_OR (1 << 4) /* rx fifo overrun */
115 #define ISR_RX (1 << 3) /* rx interrupt status */
116 #define ISR_TX (1 << 2) /* tx interrupt status */
117 #define ISR_RXTO (1 << 1) /* rx timeout */
118 #define ISR_TXC (1 << 0) /* tx complete */
123 #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
124 #define IE_UR (1 << 5) /* tx fifo underrun */
125 #define IE_OR (1 << 4) /* rx fifo overrun */
126 #define IE_RX (1 << 3) /* rx interrupt status */
127 #define IE_TX (1 << 2) /* tx interrupt status */
128 #define IE_RXTO (1 << 1) /* rx timeout */
129 #define IE_TXC (1 << 0) /* tx complete */
134 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
136 #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
137 #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */
138 #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
139 #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */
140 #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
141 #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */
142 #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
143 #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */
144 #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
145 #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */
146 #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
147 #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */