Lines Matching +full:i2s +full:- +full:input
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
10 /* i2s bus control registers, at least what we know about them */
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
89 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK)
100 if (div%2) return -1; in i2s_sf_mclkdiv()
101 d = div/2-1; in i2s_sf_mclkdiv()
103 return -1; in i2s_sf_mclkdiv()
108 /* SClk is the clock that drives the i2s wire bus. Note that it is
116 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK)
125 if (div%2) return -1; in i2s_sf_sclkdiv()
126 d = div/2-1; in i2s_sf_sclkdiv()
127 if (d == 8 || d == 9) return -1; in i2s_sf_sclkdiv()
133 /* serial format is the way the data is put to the i2s wire bus */
161 /* number of interleaved input channels */
164 /* word size of input data */