1 // SPDX-License-Identifier: GPL-2.0
27     /// Message Signaled Interrupts (MSI).
28     Msi,  enumerator
29     /// Extended Message Signaled Interrupts (MSI-X).
35     const fn as_raw(self) -> u32 {  in as_raw()
38             IrqType::Msi => bindings::PCI_IRQ_MSI,  in as_raw()
49     /// Create a set containing all IRQ types (MSI-X, MSI, and INTx).
50     pub const fn all() -> Self {  in all()
59     /// // Create a set with only MSI and MSI-X (no INTx interrupts).
61     ///     .with(IrqType::Msi)
64     pub const fn with(self, irq_type: IrqType) -> Self {  in with()
69     const fn as_raw(self) -> u32 {  in as_raw()
89     /// - `index` must be a valid IRQ vector index for `dev`.
90     /// - `dev` must point to a [`Device`] that has successfully allocated IRQ vectors.
91     unsafe fn new(dev: &'a Device<Bound>, index: u32) -> Self {  in new()
96     fn index(&self) -> u32 {  in index()
104     fn try_into(self) -> Result<IrqRequest<'a>> {  in try_into()
137     ) -> Result<RangeInclusive<IrqVector<'a>>> {  in register()
139         // - `dev.as_raw()` is guaranteed to be a valid pointer to a `struct pci_dev`  in register()
141         // - `pci_alloc_irq_vectors` internally validates all other parameters  in register()
151         // - `pci_alloc_irq_vectors` returns the number of allocated vectors on success.  in register()
152         // - Vectors are 0-based, so valid indices are [0, count-1].  in register()
153         // - `pci_alloc_irq_vectors` guarantees `count >= min_vecs > 0`, so both `0` and  in register()
154         //   `count - 1` are valid IRQ vector indices for `dev`.  in register()
155         let range = unsafe { IrqVector::new(dev, 0)..=IrqVector::new(dev, count - 1) };  in register()
168         // - By the type invariant, `self.dev.as_raw()` is a valid pointer to a `struct pci_dev`.  in drop()
169         // - `self.dev` has successfully allocated IRQ vectors.  in drop()
182     ) -> impl PinInit<irq::Registration<T>, Error> + 'a {  in request_irq()
197     ) -> impl PinInit<irq::ThreadedRegistration<T>, Error> + 'a {  in request_threaded_irq()
210     /// The allocation will use MSI-X, MSI, or INTx interrupts based on the `irq_types`
212     /// will try them in order of preference: MSI-X first, then MSI, then INTx interrupts.
219     /// * `min_vecs` - Minimum number of vectors required.
220     /// * `max_vecs` - Maximum number of vectors to allocate.
221     /// * `irq_types` - Types of interrupts that can be used.
232     /// # fn no_run(dev: &pci::Device<Bound>) -> Result {
236     /// // Allocate MSI or MSI-X only (no INTx interrupts).
238     ///     .with(pci::IrqType::Msi)
249     ) -> Result<RangeInclusive<IrqVector<'_>>> {  in alloc_irq_vectors()