Lines Matching +full:7 +full:- +full:8
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
223 vmulouw 12, 7, 1
224 vmulouw 13, 8, 0
234 vmulouw 12, 7, 2
235 vmulouw 13, 8, 1
243 vmulouw 12, 7, 3
244 vmulouw 13, 8, 2
252 vmulouw 12, 7, 26
253 vmulouw 13, 8, 3
261 vmulouw 12, 7, 27
262 vmulouw 13, 8, 26
271 vmuleuw 12, 7, 1
272 vmuleuw 13, 8, 0
282 vmuleuw 12, 7, 2
283 vmuleuw 13, 8, 1
293 vmuleuw 12, 7, 3
294 vmuleuw 13, 8, 2
304 vmuleuw 12, 7, 26
305 vmuleuw 13, 8, 3
315 vmuleuw 12, 7, 27
316 vmuleuw 13, 8, 26
361 vmr 7, 29
362 vmr 8, 30
388 vmrgow 29, 29, 7
389 vmrgow 30, 30, 8
408 xxlor 7, 34, 34
409 xxlor 8, 35, 35
445 vand 7, 17, 25
452 vand 8, 18, 25
462 vaddudm 7, 7, 13
464 vsrd 11, 7, 31
465 vand 7, 7, 25
468 vaddudm 8, 8, 11
480 ld 12, 8(10)
486 lvx 25, 0, 10 # v25 - mask
544 ld 10, 8(3)
559 vor 8, 8, 9
587 vaddudm 23, 7, 12
588 vaddudm 24, 8, 13
615 vmrgow 7, 12, 23
616 vmrgow 8, 13, 24
617 vaddudm 8, 8, 19
619 addi 5, 5, -64 # len -= 64
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
647 vand 7, 17, 25
654 vand 8, 18, 25
664 vaddudm 7, 7, 13
666 vsrd 11, 7, 31
667 vand 7, 7, 25
670 vaddudm 8, 8, 11
718 vaddudm 7, 7, 23
719 vaddudm 8, 8, 24
725 vmrgow 7, 12, 7
726 vmrgow 8, 13, 8
727 vaddudm 8, 8, 19
729 addi 5, 5, -64 # len -= 64
742 xxlor 34, 7, 7
743 xxlor 35, 8, 8
760 vaddudm 7, 17, 12
763 vaddudm 8, 18, 13
769 vsrd 11, 7, 31
770 vand 7, 7, 25
772 vaddudm 8, 8, 11
773 vsrd 12, 8, 31
777 vand 8, 8, 25
787 vaddudm 7, 7, 13
789 vsrd 11, 7, 31
790 vand 7, 7, 25
796 vaddudm 8, 8, 11
811 vsld 7, 7, 11
812 vor 21, 7, 12
814 vsld 8, 8, 11
815 vsld 8, 8, 31
816 vor 21, 21, 8
822 std 19, 8(3)
847 ld 12, 8(10)
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
878 vmsumudm 7, 6, 0, 9 # h0 * r0, h1 * s1
882 vmsumudm 10, 8, 2, 11 # d1 += h2 * s1
885 vmsumudm 11, 8, 3, 9 # d2 = h2 * r0
897 mfvsrld 27, 32+7
900 mfvsrd 20, 32+7 # h0.h
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
962 ld 28, 8(3)
976 ld 21, 8(11)
985 mtvsrdd 32+8, 29, 22 # h2
994 std 28, 8(3)
1035 ld 11, 8(3)
1039 # h + 5 + (-p)
1041 mr 7, 11
1042 mr 8, 12
1044 addze 7, 7
1045 addze 8, 8
1046 srdi 9, 8, 2 # overflow?
1050 mr 11, 7
1051 mr 12, 8
1055 ld 7, 8(4)
1057 adde 11, 11, 7
1061 std 11, 8(5)