Lines Matching full:lo
632 vmovn.i64 $D3#lo,$D3
634 vmovn.i64 $D0#lo,$D0
636 vbic.i32 $D3#lo,#0xfc000000 @ &=0x03ffffff
638 vbic.i32 $D0#lo,#0xfc000000
640 vshrn.u64 $T0#lo,$D4,#26
641 vmovn.i64 $D4#lo,$D4
643 vmovn.i64 $D1#lo,$D1
645 vbic.i32 $D4#lo,#0xfc000000
646 vbic.i32 $D1#lo,#0xfc000000
648 vadd.i32 $D0#lo,$D0#lo,$T0#lo
649 vshl.u32 $T0#lo,$T0#lo,#2
650 vshrn.u64 $T1#lo,$D2,#26
651 vmovn.i64 $D2#lo,$D2
652 vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
653 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
654 vbic.i32 $D2#lo,#0xfc000000
656 vshr.u32 $T0#lo,$D0#lo,#26
657 vbic.i32 $D0#lo,#0xfc000000
658 vshr.u32 $T1#lo,$D3#lo,#26
659 vbic.i32 $D3#lo,#0xfc000000
660 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
661 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
669 vtrn.32 $R0,$D0#lo @ r^2:r^1
670 vtrn.32 $R2,$D2#lo
671 vtrn.32 $R3,$D3#lo
672 vtrn.32 $R1,$D1#lo
673 vtrn.32 $R4,$D4#lo
698 vmov $R0,$D0#lo @ r^4:r^3
699 vshl.u32 $S1,$D1#lo,#2 @ *5
700 vmov $R1,$D1#lo
701 vshl.u32 $S2,$D2#lo,#2
702 vmov $R2,$D2#lo
703 vshl.u32 $S3,$D3#lo,#2
704 vmov $R3,$D3#lo
705 vshl.u32 $S4,$D4#lo,#2
706 vmov $R4,$D4#lo
707 vadd.i32 $S1,$S1,$D1#lo
708 vadd.i32 $S2,$S2,$D2#lo
709 vadd.i32 $S3,$S3,$D3#lo
710 vadd.i32 $S4,$S4,$D4#lo
750 veor $D0#lo,$D0#lo,$D0#lo
753 veor $D1#lo,$D1#lo,$D1#lo
756 veor $D2#lo,$D2#lo,$D2#lo
759 veor $D3#lo,$D3#lo,$D3#lo
762 veor $D4#lo,$D4#lo,$D4#lo
768 vmov.32 $D0#lo[0],r2
769 vmov.32 $D1#lo[0],r3
770 vmov.32 $D2#lo[0],r4
771 vmov.32 $D3#lo[0],r5
772 vmov.32 $D4#lo[0],r6
783 veor $D0#lo,$D0#lo,$D0#lo
784 veor $D1#lo,$D1#lo,$D1#lo
785 veor $D2#lo,$D2#lo,$D2#lo
786 veor $D3#lo,$D3#lo,$D3#lo
787 veor $D4#lo,$D4#lo,$D4#lo
788 vld4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
790 vld1.32 {$D4#lo[0]},[$ctx]
799 vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
800 vmov.32 $H4#lo[0],$padbit
810 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
811 vshl.u32 $H3#lo,$H3#lo,#18
813 vsri.u32 $H3#lo,$H2#lo,#14
814 vshl.u32 $H2#lo,$H2#lo,#12
815 vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
817 vbic.i32 $H3#lo,#0xfc000000
818 vsri.u32 $H2#lo,$H1#lo,#20
819 vshl.u32 $H1#lo,$H1#lo,#6
821 vbic.i32 $H2#lo,#0xfc000000
822 vsri.u32 $H1#lo,$H0#lo,#26
823 vadd.i32 $H3#hi,$H3#lo,$D3#lo
825 vbic.i32 $H0#lo,#0xfc000000
826 vbic.i32 $H1#lo,#0xfc000000
827 vadd.i32 $H2#hi,$H2#lo,$D2#lo
829 vadd.i32 $H0#hi,$H0#lo,$D0#lo
830 vadd.i32 $H1#hi,$H1#lo,$D1#lo
841 it lo
845 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
905 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ accumulate inp[0:1]
907 vadd.i32 $H0#lo,$H0#lo,$D0#lo
909 vadd.i32 $H3#lo,$H3#lo,$D3#lo
912 vadd.i32 $H1#lo,$H1#lo,$D1#lo
915 vadd.i32 $H4#lo,$H4#lo,$D4#lo
919 it lo
950 vmlal.u32 $D3,$H3#lo,${R0}[0]
951 vmlal.u32 $D0,$H0#lo,${R0}[0]
952 vmlal.u32 $D4,$H4#lo,${R0}[0]
953 vmlal.u32 $D1,$H1#lo,${R0}[0]
954 vmlal.u32 $D2,$H2#lo,${R0}[0]
957 vmlal.u32 $D3,$H2#lo,${R1}[0]
958 vmlal.u32 $D0,$H4#lo,${S1}[0]
959 vmlal.u32 $D4,$H3#lo,${R1}[0]
960 vmlal.u32 $D1,$H0#lo,${R1}[0]
961 vmlal.u32 $D2,$H1#lo,${R1}[0]
963 vmlal.u32 $D3,$H1#lo,${R2}[0]
964 vmlal.u32 $D0,$H3#lo,${S2}[0]
965 vmlal.u32 $D4,$H2#lo,${R2}[0]
966 vmlal.u32 $D1,$H4#lo,${S2}[0]
967 vmlal.u32 $D2,$H0#lo,${R2}[0]
969 vmlal.u32 $D3,$H0#lo,${R3}[0]
970 vmlal.u32 $D0,$H2#lo,${S3}[0]
971 vmlal.u32 $D4,$H1#lo,${R3}[0]
972 vmlal.u32 $D1,$H3#lo,${S3}[0]
973 vmlal.u32 $D3,$H4#lo,${S4}[0]
975 vmlal.u32 $D2,$H4#lo,${S3}[0]
976 vmlal.u32 $D0,$H1#lo,${S4}[0]
977 vmlal.u32 $D4,$H0#lo,${R4}[0]
979 vmlal.u32 $D1,$H2#lo,${S4}[0]
980 vmlal.u32 $D2,$H3#lo,${S4}[0]
982 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
996 vmovn.i64 $D3#lo,$D3
998 vmovn.i64 $D0#lo,$D0
1000 vbic.i32 $D3#lo,#0xfc000000
1004 vbic.i32 $D0#lo,#0xfc000000
1006 vshrn.u64 $T0#lo,$D4,#26
1007 vmovn.i64 $D4#lo,$D4
1009 vmovn.i64 $D1#lo,$D1
1012 vbic.i32 $D4#lo,#0xfc000000
1014 vbic.i32 $D1#lo,#0xfc000000
1016 vadd.i32 $D0#lo,$D0#lo,$T0#lo
1017 vshl.u32 $T0#lo,$T0#lo,#2
1019 vshrn.u64 $T1#lo,$D2,#26
1020 vmovn.i64 $D2#lo,$D2
1021 vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
1023 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
1025 vbic.i32 $D2#lo,#0xfc000000
1028 vshrn.u64 $T0#lo,$D0,#26 @ re-narrow
1029 vmovn.i64 $D0#lo,$D0
1032 vshr.u32 $T1#lo,$D3#lo,#26
1033 vbic.i32 $D3#lo,#0xfc000000
1034 vbic.i32 $D0#lo,#0xfc000000
1035 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
1036 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
1052 vadd.i32 $H2#hi,$H2#lo,$D2#lo @ add hash value and move to #hi
1053 vadd.i32 $H0#hi,$H0#lo,$D0#lo
1054 vadd.i32 $H3#hi,$H3#lo,$D3#lo
1055 vadd.i32 $H1#hi,$H1#lo,$D1#lo
1056 vadd.i32 $H4#hi,$H4#lo,$D4#lo
1062 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ can be redundant
1064 vadd.i32 $H0#lo,$H0#lo,$D0#lo
1066 vadd.i32 $H3#lo,$H3#lo,$D3#lo
1068 vadd.i32 $H1#lo,$H1#lo,$D1#lo
1070 vadd.i32 $H4#lo,$H4#lo,$D4#lo
1115 vmlal.u32 $D2,$H2#lo,$R0
1116 vmlal.u32 $D0,$H0#lo,$R0
1117 vmlal.u32 $D3,$H3#lo,$R0
1118 vmlal.u32 $D1,$H1#lo,$R0
1119 vmlal.u32 $D4,$H4#lo,$R0
1121 vmlal.u32 $D0,$H4#lo,$S1
1123 vmlal.u32 $D3,$H2#lo,$R1
1125 vmlal.u32 $D1,$H0#lo,$R1
1126 vmlal.u32 $D4,$H3#lo,$R1
1127 vmlal.u32 $D2,$H1#lo,$R1
1129 vmlal.u32 $D3,$H1#lo,$R2
1131 vmlal.u32 $D0,$H3#lo,$S2
1133 vmlal.u32 $D4,$H2#lo,$R2
1134 vmlal.u32 $D1,$H4#lo,$S2
1135 vmlal.u32 $D2,$H0#lo,$R2
1137 vmlal.u32 $D3,$H0#lo,$R3
1138 vmlal.u32 $D0,$H2#lo,$S3
1139 vmlal.u32 $D4,$H1#lo,$R3
1140 vmlal.u32 $D1,$H3#lo,$S3
1141 vmlal.u32 $D2,$H4#lo,$S3
1143 vmlal.u32 $D3,$H4#lo,$S4
1145 vmlal.u32 $D0,$H1#lo,$S4
1147 vmlal.u32 $D4,$H0#lo,$R4
1148 vmlal.u32 $D1,$H2#lo,$S4
1149 vmlal.u32 $D2,$H3#lo,$S4
1155 vadd.i64 $D3#lo,$D3#lo,$D3#hi
1156 vadd.i64 $D0#lo,$D0#lo,$D0#hi
1157 vadd.i64 $D4#lo,$D4#lo,$D4#hi
1158 vadd.i64 $D1#lo,$D1#lo,$D1#hi
1159 vadd.i64 $D2#lo,$D2#lo,$D2#hi
1197 vst4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
1198 vst1.32 {$D4#lo[0]},[$ctx]
1229 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or