Lines Matching +full:row +full:- +full:hold

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 	// Registers used to hold message words temporarily.  There aren't
17 	// enough ARM registers to hold the whole message block, so we have to
18 	// load the words on-demand.
62 // Execute a quarter-round of BLAKE2s by mixing two columns or two diagonals.
64 // columns/diagonals.  s0-s1 are the word offsets to the message words the first
65 // column/diagonal needs, and likewise s2-s3 for the second column/diagonal.
118 // spilling v[8..9], then to v[9..15], then to the message block.  r10-r12 and
119 // r14 are free to use.  The macro arguments s0-s15 give the order in which the
127 // when the values are used.  'brot' is the number of bits the values in row 'b'
129 // similarly for row 'd'.  (brot, drot) start out as (0, 0) but we make it such
183 	push		{r0-r2,r4-r11,lr}	// keep this an even number
203 	ldmia		r1!, {r2-r9}
205 	stmia		r12!, {r2-r9}
206 	ldmia		r1!, {r2-r9}
208 	stmia		r12, {r2-r9}
213 	// for spilling v[8..9].  Leave v[8..9] in r8-r9.
216 	ldmia		r12!, {r8-r9}		// load IV[0..1]
218 	ldm		r12, {r2-r7}		// load IV[3..7]
223 	push		{r2-r7}			// push v[9..15]
227 	ldm		r14, {r0-r7}
251 	pop		{r10-r11}		// load v[10..11]
256 	ldm		r14, {r8-r11}		// load h[0..3]
261 	stmia		r14!, {r0-r3}		// store new h[0..3]
262 	ldm		r14, {r0-r3}		// load old h[4..7]
263 	pop		{r8-r11}		// load v[12..15]
273 	stm		r14, {r0-r3}		// store new h[4..7]
277 	// 64.  So we can simply set it to 64 without re-loading it.
280 	subs		r2, r2, #1		// nblocks--
284 	pop		{r0-r2,r4-r11,pc}
286 	// The next message block (pointed to by r1) isn't 4-byte aligned, so it
288 	// by r12) using an alternative method.  r2-r9 are free to use.