35  *	R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
36  *	R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
37  *	R3 = [(x128+32 mod P'(x) << 32)]'   << 1
38  *	R4 = [(x128-32 mod P'(x) << 32)]'   << 1
39  *	R5 = [(x64 mod P'(x) << 32)]'	    << 1
40  *	R6 = [(x32 mod P'(x) << 32)]'	    << 1
65 	0x0, 0x1db710641			/* P'(x) << 1 */
74 	0x0, 0x105ec76f0			/* P'(x) << 1 */
87  *	V1..V4:	  Data for CRC computation.
108 	fpu_vlm(1, 4, buf);  in crc32_le_vgfm_generic()
109 	fpu_vperm(1, 1, 1, CONST_PERM_LE2BE);  in crc32_le_vgfm_generic()
114 	fpu_vx(1, 0, 1);		/* V1 ^= CRC */  in crc32_le_vgfm_generic()
125 		 * Perform a GF(2) multiplication of the doublewords in V1 with  in crc32_le_vgfm_generic()
128 		 * in V5 and stored in V1. Repeat this step for the register  in crc32_le_vgfm_generic()
131 		fpu_vgfmag(1, CONST_R2R1, 1, 5);  in crc32_le_vgfm_generic()
140 	 * Fold V1 to V4 into a single 128-bit value in V1.  Multiply V1 with R3  in crc32_le_vgfm_generic()
144 	fpu_vgfmag(1, CONST_R4R3, 1, 2);  in crc32_le_vgfm_generic()
145 	fpu_vgfmag(1, CONST_R4R3, 1, 3);  in crc32_le_vgfm_generic()
146 	fpu_vgfmag(1, CONST_R4R3, 1, 4);  in crc32_le_vgfm_generic()
151 		fpu_vgfmag(1, CONST_R4R3, 1, 2);  in crc32_le_vgfm_generic()
158 	 * be loaded in bits 1-4 in byte element 7 of a vector register.  in crc32_le_vgfm_generic()
170 	fpu_vleig(0, 1, 0);  in crc32_le_vgfm_generic()
173 	 * Compute GF(2) product of V1 and V0.	The rightmost doubleword  in crc32_le_vgfm_generic()
174 	 * of V1 is multiplied with R4.  The leftmost doubleword of V1 is  in crc32_le_vgfm_generic()
178 	fpu_vgfmg(1, 0, 1);  in crc32_le_vgfm_generic()
182 	 * in V1 with R5 and XOR the result with the remaining bits in V1.  in crc32_le_vgfm_generic()
184 	 * To achieve this by a single VGFMAG, right shift V1 by a word  in crc32_le_vgfm_generic()
187 	 * doubleword into the rightmost doubleword element of V1; the other  in crc32_le_vgfm_generic()
191 	 * the leftmost product of V1.  in crc32_le_vgfm_generic()
194 	fpu_vsrlb(2, 1, 9);		  /* Store remaining bits in V2 */  in crc32_le_vgfm_generic()
195 	fpu_vupllf(1, 1);		  /* Split rightmost doubleword */  in crc32_le_vgfm_generic()
196 	fpu_vgfmag(1, CONST_R5, 1, 2);	  /* V1 = (V1 * R5) XOR V2 */  in crc32_le_vgfm_generic()
202 	 * in V1 (R(x)), degree-32 generator polynomial, and the reduction  in crc32_le_vgfm_generic()
208 	 *    1. T1(x) = floor( R(x) / x^32 ) GF2MUL u  in crc32_le_vgfm_generic()
218 	fpu_vupllf(2, 1);  in crc32_le_vgfm_generic()
223 	 * V2 and XOR the intermediate result, T2(x), with the value in V1.  in crc32_le_vgfm_generic()
227 	fpu_vgfmag(2, CONST_CRC_POLY, 2, 1);  in crc32_le_vgfm_generic()