Lines Matching full:barrier
13 * barrier before sending the IPI
19 * The memory barrier at the start of membarrier() on CPU0 is necessary in
22 * CPU1 after the IPI-induced memory barrier:
33 * barrier()
40 * point after (b). If the memory barrier at (a) is omitted, then "x = 1"
45 * The timing of the memory barrier at (a) has to ensure that it executes
46 * before the IPI-induced memory barrier on CPU1.
49 * barrier after completing the IPI
55 * The memory barrier at the end of membarrier() on CPU0 is necessary in
63 * barrier()
75 * the memory barrier at (c) is omitted then "r1 = x" can be reordered
79 * The timing of the memory barrier at (c) has to ensure that it executes
80 * after the IPI-induced memory barrier on CPU1.
212 * Issue a memory barrier after setting in ipi_sync_rq_state()
223 * Issue a memory barrier before clearing membarrier_state to in membarrier_exec_mmap()
306 * Memory barrier on the caller thread _after_ we finished in membarrier_global_expedited()
350 * On RISC-V, this barrier pairing is also needed for the in membarrier_private_expedited()
399 * and the new cpu will execute a full barrier in the in membarrier_private_expedited()
402 * For SYNC_CORE, we do need a barrier on the current cpu -- in membarrier_private_expedited()
427 * Memory barrier on the caller thread _after_ we finished in membarrier_private_expedited()
446 * For single mm user, we can simply issue a memory barrier in sync_runqueues_membarrier_state()
612 * the semantic "barrier()" to represent a compiler barrier forcing memory
613 * accesses to be performed in program order across the barrier, and
615 * ordering across the barrier, we have the following ordering table for
616 * each pair of barrier(), sys_membarrier() and smp_mb():
620 * barrier() smp_mb() sys_membarrier()
621 * barrier() X X O