Lines Matching defs:gc
39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
43 irq_gc_lock(gc);
44 irq_reg_writel(gc, mask, ct->regs.disable);
46 irq_gc_unlock(gc);
55 * and protected by gc->lock
59 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
63 irq_gc_lock(gc);
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
66 irq_gc_unlock(gc);
75 * and protected by gc->lock
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
83 irq_gc_lock(gc);
85 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
86 irq_gc_unlock(gc);
99 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
103 irq_gc_lock(gc);
104 irq_reg_writel(gc, mask, ct->regs.enable);
106 irq_gc_unlock(gc);
116 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
120 irq_gc_lock(gc);
121 irq_reg_writel(gc, mask, ct->regs.ack);
122 irq_gc_unlock(gc);
132 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
136 irq_gc_lock(gc);
137 irq_reg_writel(gc, mask, ct->regs.ack);
138 irq_gc_unlock(gc);
155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
159 irq_gc_lock(gc);
160 irq_reg_writel(gc, mask, ct->regs.disable);
162 irq_reg_writel(gc, mask, ct->regs.ack);
163 irq_gc_unlock(gc);
173 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
177 irq_gc_lock(gc);
178 irq_reg_writel(gc, mask, ct->regs.eoi);
179 irq_gc_unlock(gc);
193 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
196 if (!(mask & gc->wake_enabled))
199 irq_gc_lock(gc);
201 gc->wake_active |= mask;
203 gc->wake_active &= ~mask;
204 irq_gc_unlock(gc);
219 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
223 struct irq_chip_type *ct = gc->chip_types;
226 raw_spin_lock_init(&gc->lock);
227 gc->num_ct = num_ct;
228 gc->irq_base = irq_base;
229 gc->reg_base = reg_base;
232 gc->chip_types->handler = handler;
250 struct irq_chip_generic *gc;
252 gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
253 if (gc) {
254 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
257 return gc;
262 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
264 struct irq_chip_type *ct = gc->chip_types;
265 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
268 for (i = 0; i < gc->num_ct; i++) {
275 *mskptr = irq_reg_readl(gc, mskreg);
290 struct irq_chip_generic *gc;
299 if (d->gc)
307 gc_sz = struct_size(gc, chip_types, info->num_ct);
308 dgc_sz = struct_size(dgc, gc, numchips);
320 d->gc = dgc;
326 dgc->gc[i] = gc = tmp;
327 irq_init_generic_chip(gc, info->name, info->num_ct,
331 gc->domain = d;
333 gc->reg_readl = &irq_readl_be;
334 gc->reg_writel = &irq_writel_be;
338 ret = info->init(gc);
344 list_add_tail(&gc->list, &gc_list);
354 dgc->exit(dgc->gc[i]);
355 irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0);
357 d->gc = NULL;
369 struct irq_domain_chip_generic *dgc = d->gc;
377 dgc->exit(dgc->gc[i]);
378 irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0);
380 d->gc = NULL;
419 struct irq_domain_chip_generic *dgc = d->gc;
427 return dgc->gc[idx];
438 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
440 return !IS_ERR(gc) ? gc : NULL;
458 struct irq_domain_chip_generic *dgc = d->gc;
459 struct irq_chip_generic *gc;
465 gc = __irq_get_domain_generic_chip(d, hw_irq);
466 if (IS_ERR(gc))
467 return PTR_ERR(gc);
471 if (test_bit(idx, &gc->unused))
474 if (test_bit(idx, &gc->installed))
477 ct = gc->chip_types;
481 if (!gc->installed) {
482 raw_spin_lock_irqsave(&gc->lock, flags);
483 irq_gc_init_mask_cache(gc, dgc->gc_flags);
484 raw_spin_unlock_irqrestore(&gc->lock, flags);
488 set_bit(idx, &gc->installed);
499 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
507 struct irq_domain_chip_generic *dgc = d->gc;
509 struct irq_chip_generic *gc;
512 gc = irq_get_domain_generic_chip(d, hw_irq);
513 if (!gc)
518 clear_bit(irq_idx, &gc->installed);
533 * @gc: Generic irq chip holding all data
534 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
539 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
543 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
547 struct irq_chip_type *ct = gc->chip_types;
552 list_add_tail(&gc->list, &gc_list);
555 irq_gc_init_mask_cache(gc, flags);
557 for (i = gc->irq_base; msk; msk >>= 1, i++) {
571 d->mask = 1 << (i - gc->irq_base);
574 irq_set_chip_data(i, gc);
577 gc->irq_cnt = i - gc->irq_base;
590 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
591 struct irq_chip_type *ct = gc->chip_types;
594 for (i = 0; i < gc->num_ct; i++, ct++) {
607 * @gc: Generic irq chip holding all data
608 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
612 * Remove up to 32 interrupts starting from gc->irq_base.
614 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
620 list_del(&gc->list);
629 * interrupt number in gc::irq_base. Otherwise gc::irq_base
632 if (gc->domain) {
633 virq = irq_find_mapping(gc->domain, gc->irq_base + i);
637 virq = gc->irq_base + i;
649 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
653 if (!gc->domain)
654 return irq_get_irq_data(gc->irq_base);
660 if (!gc->installed)
663 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
670 struct irq_chip_generic *gc;
672 list_for_each_entry(gc, &gc_list, list) {
673 struct irq_chip_type *ct = gc->chip_types;
676 struct irq_data *data = irq_gc_get_irq_data(gc);
682 if (gc->suspend)
683 gc->suspend(gc);
690 struct irq_chip_generic *gc;
692 list_for_each_entry(gc, &gc_list, list) {
693 struct irq_chip_type *ct = gc->chip_types;
695 if (gc->resume)
696 gc->resume(gc);
699 struct irq_data *data = irq_gc_get_irq_data(gc);
713 struct irq_chip_generic *gc;
715 list_for_each_entry(gc, &gc_list, list) {
716 struct irq_chip_type *ct = gc->chip_types;
719 struct irq_data *data = irq_gc_get_irq_data(gc);