Lines Matching +full:0 +full:x02d0
27 # define SST_DEBUG_REG 0
28 # define SST_DEBUG_FUNC 0
29 # define SST_DEBUG_VAR 0
32 #if (SST_DEBUG_REG > 0)
43 #if (SST_DEBUG_FUNC > 0)
59 #if (SST_DEBUG_VAR > 0)
81 #define PCI_INIT_ENABLE 0x40
82 # define PCI_EN_INIT_WR BIT(0)
85 #define PCI_VCLK_ENABLE 0xc0 /* enable video */
86 #define PCI_VCLK_DISABLE 0xe0
89 #define STATUS 0x0000
91 #define FBZMODE 0x0110
92 # define EN_CLIPPING BIT(0) /* enable clipping */
96 #define LFBMODE 0x0114
97 # define LFB_565 0 /* bits 3:0 .16 bits RGB */
100 # define WR_BUFF_FRONT 0 /* write buf select (front) */
102 # define RD_BUFF_FRONT 0 /* read buff select (front) */
110 #define CLIP_LEFT_RIGHT 0x0118
111 #define CLIP_LOWY_HIGHY 0x011c
112 #define NOPCMD 0x0120
113 #define FASTFILLCMD 0x0124
114 #define SWAPBUFFCMD 0x0128
115 #define FBIINIT4 0x0200 /* misc controls */
116 # define FAST_PCI_READS 0 /* 1 waitstate */
117 # define SLOW_PCI_READS BIT(0) /* 2 ws */
119 #define BACKPORCH 0x0208
120 #define VIDEODIMENSIONS 0x020c
121 #define FBIINIT0 0x0210 /* misc+fifo controls */
122 # define DIS_VGA_PASSTHROUGH BIT(0)
125 #define FBIINIT1 0x0214 /* PCI + video controls */
126 # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/
127 # define FAST_PCI_WRITES 0 /* 0 ws */
137 # define SEL_INPUT_VCLK_2X 0 /* bit 17 */
139 # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */
140 # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
141 # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20)
144 # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */
146 #define FBIINIT2 0x0218 /* Dram controls */
151 # define SWAP_DACVSYNC 0
156 # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */
158 #define FBIINIT3 0x021c /* fbi controls */
161 #define HSYNC 0x0220
162 #define VSYNC 0x0224
163 #define DAC_DATA 0x022c
165 #define FBIINIT5 0x0244 /* v2 specific */
166 # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/
172 #define FBIINIT6 0x0248 /* v2 specific */
174 #define FBIINIT7 0x024c /* v2 specific */
176 #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
177 #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */
178 #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
179 #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
180 #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */
181 #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */
182 #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */
183 #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
184 #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */
185 #define BLTSIZE 0x02e8 /* BitBLT width and height */
186 #define BLTROP 0x02ec /* BitBLT Raster operations */
187 # define BLTROP_COPY 0x0cccc
188 # define BLTROP_INVERT 0x05555
189 # define BLTROP_XOR 0x06666
190 #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */
191 #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */
192 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
196 #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
200 #define DACREG_WMA 0x0 /* pixel write mode address */
201 #define DACREG_LUT 0x01 /* color value */
202 #define DACREG_RMR 0x02 /* pixel mask */
203 #define DACREG_RMA 0x03 /* pixel read mode address */
207 #define DACREG_RMR_I 0x00
208 #define DACREG_CR0_I 0x01
209 # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
212 # define DACREG_CR0_16BPP 0x30 /* mode 3 */
213 # define DACREG_CR0_24BPP 0x50 /* mode 5 */
214 #define DACREG_CR1_I 0x05
215 #define DACREG_CC_I 0x06
220 #define DACREG_AC0_I 0x48 /* clock A reg C */
221 #define DACREG_AC1_I 0x49
222 #define DACREG_BD0_I 0x6c /* clock B reg D */
223 #define DACREG_BD1_I 0x6d
226 #define DACREG_MIR_TI 0x97
227 #define DACREG_DIR_TI 0x09
228 #define DACREG_MIR_ATT 0x84
229 #define DACREG_DIR_ATT 0x09
231 #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
232 #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
233 #define DACREG_ICS_CMD 0x06 /* command */
234 # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
235 # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
236 # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
237 #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
242 * 8 freq registers (0-7) for video clock (CLK0)
245 #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
246 #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */
247 #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */
248 #define DACREG_ICS_PLL_CTRL 0x0e
250 # define DACREG_ICS_CLK0_0 0
251 # define DACREG_ICS_CLK1_A 0 /* bit4 */
291 #define FBIINIT6_DEFAULT (0x0)
300 #define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32)
301 #define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32)
306 VID_CLOCK=0,
353 u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */