Lines Matching +full:display +full:- +full:timing
4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
40 #define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
41 #define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
48 #define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
53 #define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
61 #define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
67 #define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
68 #define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
69 #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
73 #define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
74 #define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
75 #define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
76 #define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
80 #define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
81 #define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
128 #define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
129 #define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
130 #define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
133 #define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
134 #define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
152 unsigned char display; member