Lines Matching +full:0 +full:x00280000

34 #define DM1_PLANES         0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
45 #define NPORT_DMODE1_DD12 0x00000010
46 #define NPORT_DMODE1_DD24 0x00000018
47 #define NPORT_DMODE1_DSRC 0x00000020
48 #define NPORT_DMODE1_YFLIP 0x00000040
49 #define NPORT_DMODE1_RWPCKD 0x00000080
50 #define NPORT_DMODE1_HDMASK 0x00000300
51 #define NPORT_DMODE1_HD4 0x00000000
52 #define NPORT_DMODE1_HD8 0x00000100
53 #define NPORT_DMODE1_HD12 0x00000200
54 #define NPORT_DMODE1_HD32 0x00000300
55 #define NPORT_DMODE1_RWDBL 0x00000400
56 #define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */
57 #define NPORT_DMODE1_CCMASK 0x00007000
58 #define NPORT_DMODE1_CCLT 0x00001000
59 #define NPORT_DMODE1_CCEQ 0x00002000
60 #define NPORT_DMODE1_CCGT 0x00004000
61 #define NPORT_DMODE1_RGBMD 0x00008000
62 #define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */
63 #define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */
64 #define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */
65 #define NPORT_DMODE1_SFMASK 0x00380000
66 #define NPORT_DMODE1_SF0 0x00000000
67 #define NPORT_DMODE1_SF1 0x00080000
68 #define NPORT_DMODE1_SFDC 0x00100000
69 #define NPORT_DMODE1_SFMDC 0x00180000
70 #define NPORT_DMODE1_SFSA 0x00200000
71 #define NPORT_DMODE1_SFMSA 0x00280000
72 #define NPORT_DMODE1_DFMASK 0x01c00000
73 #define NPORT_DMODE1_DF0 0x00000000
74 #define NPORT_DMODE1_DF1 0x00400000
75 #define NPORT_DMODE1_DFSC 0x00800000
76 #define NPORT_DMODE1_DFMSC 0x00c00000
77 #define NPORT_DMODE1_DFSA 0x01000000
78 #define NPORT_DMODE1_DFMSA 0x01400000
79 #define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */
80 #define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */
81 #define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */
82 #define NPORT_DMODE1_LOMASK 0xf0000000
83 #define NPORT_DMODE1_LOZERO 0x00000000
84 #define NPORT_DMODE1_LOAND 0x10000000
85 #define NPORT_DMODE1_LOANDR 0x20000000
86 #define NPORT_DMODE1_LOSRC 0x30000000
87 #define NPORT_DMODE1_LOANDI 0x40000000
88 #define NPORT_DMODE1_LODST 0x50000000
89 #define NPORT_DMODE1_LOXOR 0x60000000
90 #define NPORT_DMODE1_LOOR 0x70000000
91 #define NPORT_DMODE1_LONOR 0x80000000
92 #define NPORT_DMODE1_LOXNOR 0x90000000
93 #define NPORT_DMODE1_LONDST 0xa0000000
94 #define NPORT_DMODE1_LOORR 0xb0000000
95 #define NPORT_DMODE1_LONSRC 0xc0000000
96 #define NPORT_DMODE1_LOORI 0xd0000000
97 #define NPORT_DMODE1_LONAND 0xe0000000
98 #define NPORT_DMODE1_LOONE 0xf0000000
103 #define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */
104 #define NPORT_DMODE0_NOP 0x00000000 /* No operation */
105 #define NPORT_DMODE0_RD 0x00000001 /* Read operation */
106 #define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */
107 #define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */
110 #define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */
111 #define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */
112 #define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */
113 #define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */
114 #define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */
115 #define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */
116 #define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */
117 #define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */
120 #define NPORT_DMODE0_DOSETUP 0x00000020
121 #define NPORT_DMODE0_CHOST 0x00000040
122 #define NPORT_DMODE0_AHOST 0x00000080
123 #define NPORT_DMODE0_STOPX 0x00000100
124 #define NPORT_DMODE0_STOPY 0x00000200
125 #define NPORT_DMODE0_SK1ST 0x00000400
126 #define NPORT_DMODE0_SKLST 0x00000800
127 #define NPORT_DMODE0_ZPENAB 0x00001000
128 #define NPORT_DMODE0_LISPENAB 0x00002000
129 #define NPORT_DMODE0_LISLST 0x00004000
130 #define NPORT_DMODE0_L32 0x00008000
131 #define NPORT_DMODE0_ZOPQ 0x00010000
132 #define NPORT_DMODE0_LISOPQ 0x00020000
133 #define NPORT_DMODE0_SHADE 0x00040000
134 #define NPORT_DMODE0_LRONLY 0x00080000
135 #define NPORT_DMODE0_XYOFF 0x00100000
136 #define NPORT_DMODE0_CLAMP 0x00200000
137 #define NPORT_DMODE0_ENDPF 0x00400000
138 #define NPORT_DMODE0_YSTR 0x00800000
148 npireg_t smask0x; /* Window GL relative screen mask 0 */
149 npireg_t smask0y; /* Window GL relative screen mask 0 */
155 unsigned int _pad1[0x30];
182 unsigned int _unused2[0x29];
199 #define NPORT_DMODE_WMASK 0x00000003
200 #define NPORT_DMODE_W4 0x00000000
201 #define NPORT_DMODE_W1 0x00000001
202 #define NPORT_DMODE_W2 0x00000002
203 #define NPORT_DMODE_W3 0x00000003
204 #define NPORT_DMODE_EDPACK 0x00000004
205 #define NPORT_DMODE_ECINC 0x00000008
206 #define NPORT_DMODE_CMASK 0x00000070
207 #define NPORT_DMODE_AMASK 0x00000780
208 #define NPORT_DMODE_AVC2 0x00000000
209 #define NPORT_DMODE_ACMALL 0x00000080
210 #define NPORT_DMODE_ACM0 0x00000100
211 #define NPORT_DMODE_ACM1 0x00000180
212 #define NPORT_DMODE_AXMALL 0x00000200
213 #define NPORT_DMODE_AXM0 0x00000280
214 #define NPORT_DMODE_AXM1 0x00000300
215 #define NPORT_DMODE_ABT 0x00000380
216 #define NPORT_DMODE_AVCC1 0x00000400
217 #define NPORT_DMODE_AVAB1 0x00000480
218 #define NPORT_DMODE_ALG3V0 0x00000500
219 #define NPORT_DMODE_A1562 0x00000580
220 #define NPORT_DMODE_ESACK 0x00000800
221 #define NPORT_DMODE_EASACK 0x00001000
222 #define NPORT_DMODE_CWMASK 0x0003e000
223 #define NPORT_DMODE_CHMASK 0x007c0000
224 #define NPORT_DMODE_CSMASK 0x0f800000
225 #define NPORT_DMODE_SENDIAN 0x10000000
245 #define NPORT_CMODE_SM0 0x00000001
246 #define NPORT_CMODE_SM1 0x00000002
247 #define NPORT_CMODE_SM2 0x00000004
248 #define NPORT_CMODE_SM3 0x00000008
249 #define NPORT_CMODE_SM4 0x00000010
250 #define NPORT_CMODE_CMSK 0x00001e00
254 #define NPORT_CFG_G32MD 0x00000001
255 #define NPORT_CFG_BWIDTH 0x00000002
256 #define NPORT_CFG_ERCVR 0x00000004
257 #define NPORT_CFG_BDMSK 0x00000078
258 #define NPORT_CFG_BFAINT 0x00000080
259 #define NPORT_CFG_GDMSK 0x00001f80
260 #define NPORT_CFG_GD0 0x00000100
261 #define NPORT_CFG_GD1 0x00000200
262 #define NPORT_CFG_GD2 0x00000400
263 #define NPORT_CFG_GD3 0x00000800
264 #define NPORT_CFG_GD4 0x00001000
265 #define NPORT_CFG_GFAINT 0x00002000
266 #define NPORT_CFG_TOMSK 0x0001c000
267 #define NPORT_CFG_VRMSK 0x000e0000
268 #define NPORT_CFG_FBTYP 0x00100000
272 #define NPORT_STAT_VERS 0x00000007
273 #define NPORT_STAT_GBUSY 0x00000008
274 #define NPORT_STAT_BBUSY 0x00000010
275 #define NPORT_STAT_VRINT 0x00000020
276 #define NPORT_STAT_VIDINT 0x00000040
277 #define NPORT_STAT_GLMSK 0x00001f80
278 #define NPORT_STAT_BLMSK 0x0007e000
279 #define NPORT_STAT_BFIRQ 0x00080000
280 #define NPORT_STAT_GFIRQ 0x00100000
288 unsigned int _unused0[0x16e];
290 unsigned int _unused1[0x22e];
292 unsigned int _unused2[0x1ef];
357 #define VC2_REGADDR_INDEX 0x00000000
358 #define VC2_REGADDR_IREG 0x00000010
359 #define VC2_REGADDR_RAM 0x00000030
360 #define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
362 #define VC2_VLINET_ADDR 0x000
363 #define VC2_VFRAMET_ADDR 0x400
364 #define VC2_CGLYPH_ADDR 0x500
367 #define VC2_IREG_VENTRY 0x00
368 #define VC2_IREG_CENTRY 0x01
369 #define VC2_IREG_CURSX 0x02
370 #define VC2_IREG_CURSY 0x03
371 #define VC2_IREG_CCURSX 0x04
372 #define VC2_IREG_DENTRY 0x05
373 #define VC2_IREG_SLEN 0x06
374 #define VC2_IREG_RADDR 0x07
375 #define VC2_IREG_VFPTR 0x08
376 #define VC2_IREG_VLSPTR 0x09
377 #define VC2_IREG_VLIR 0x0a
378 #define VC2_IREG_VLCTR 0x0b
379 #define VC2_IREG_CTPTR 0x0c
380 #define VC2_IREG_WCURSY 0x0d
381 #define VC2_IREG_DFPTR 0x0e
382 #define VC2_IREG_DLTPTR 0x0f
383 #define VC2_IREG_CONTROL 0x10
384 #define VC2_IREG_CONFIG 0x20
407 #define VC2_CTRL_EVIRQ 0x0001
408 #define VC2_CTRL_EDISP 0x0002
409 #define VC2_CTRL_EVIDEO 0x0004
410 #define VC2_CTRL_EDIDS 0x0008
411 #define VC2_CTRL_ECURS 0x0010
412 #define VC2_CTRL_EGSYNC 0x0020
413 #define VC2_CTRL_EILACE 0x0040
414 #define VC2_CTRL_ECDISP 0x0080
415 #define VC2_CTRL_ECCURS 0x0100
416 #define VC2_CTRL_ECG64 0x0200
417 #define VC2_CTRL_GLSEL 0x0400
420 #define NCMAP_REGADDR_AREG 0x00000000
421 #define NCMAP_REGADDR_ALO 0x00000000
422 #define NCMAP_REGADDR_AHI 0x00000010
423 #define NCMAP_REGADDR_PBUF 0x00000020
424 #define NCMAP_REGADDR_CREG 0x00000030
425 #define NCMAP_REGADDR_SREG 0x00000040
426 #define NCMAP_REGADDR_RREG 0x00000060
427 #define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)
478 #define DCB_DATAWIDTH_4 0x0
479 #define DCB_DATAWIDTH_1 0x1
480 #define DCB_DATAWIDTH_2 0x2
481 #define DCB_DATAWIDTH_3 0x3
494 #define DCB_VC2 (0 << DCB_ADDR_SHIFT)
518 # define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)
519 # define XM9_PUPMODE (1 << 0)
528 # define XM9_FIFO_0_AVAIL 0
545 #define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)
546 #define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)
547 #define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
573 rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff); in xmap9SetModeReg()
578 #define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)
581 #define BT445_REVISION_REG 0x01