Lines Matching +full:stream +full:- +full:match +full:- +full:mask
1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
81 * - &DRM_IOCTL_XE_EXEC
82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE
83 * - &DRM_IOCTL_XE_OBSERVATION
84 * - &DRM_IOCTL_XE_MADVISE
85 * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
110 /* Must be kept compact -- no holes */
147 * .. code-block:: C
168 * struct drm_xe_user_extension - Base class for defining a chain of extensions
198 * struct drm_xe_ext_set_property - Generic set property extension
221 * struct drm_xe_engine_class_instance - instance of an engine class
228 * - %DRM_XE_ENGINE_CLASS_RENDER
229 * - %DRM_XE_ENGINE_CLASS_COPY
230 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
231 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
232 * - %DRM_XE_ENGINE_CLASS_COMPUTE
233 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
255 * struct drm_xe_engine - describe hardware engine
266 * struct drm_xe_query_engines - describe engines
282 * enum drm_xe_memory_class - Supported memory classes.
296 * struct drm_xe_mem_region - Describes some region as known to
313 * @min_page_size: Min page-size in bytes for this region.
322 * Affected IOCTLS will return %-EINVAL if alignment restrictions are
372 * struct drm_xe_query_mem_regions - describe memory regions
388 * struct drm_xe_query_config - describe the device configuration
395 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
397 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
400 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
402 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device
404 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
406 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
408 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
409 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
432 * struct drm_xe_gt - describe an individual GT.
440 * - %DRM_XE_QUERY_GT_TYPE_MAIN
441 * - %DRM_XE_QUERY_GT_TYPE_MEDIA
457 * @near_mem_regions: Bit mask of instances from
460 * Each index in this mask refers directly to the struct
467 * @far_mem_regions: Bit mask of instances from
472 * Each index in this mask refers directly to the struct
491 * struct drm_xe_query_gt_list - A list with GT description items.
507 * struct drm_xe_query_topology_mask - describe the topology mask of a GT
517 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
519 * containing the following in mask:
522 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
524 * containing the following in mask:
527 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type
528 * may be omitted if the driver is unable to query the mask from the
530 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
532 * containing the following in mask:
536 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
538 * response containing the following in mask:
544 /** @gt_id: GT ID the mask is associated with */
552 /** @type: type of mask */
555 /** @num_bytes: number of bytes in requested mask */
558 /** @mask: little-endian mask of @num_bytes */
559 __u8 mask[];
563 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
614 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
617 * of the micro-controller firmware.
620 /** @uc_type: The micro-controller type to query firmware version */
645 * struct drm_xe_query_pxp_status - query if PXP is ready
654 * -ENODEV: PXP not supported or disabled;
655 * -EIO: fatal error occurred during init, so PXP will never be enabled;
656 * -EINVAL: incorrect value provided as part of the query;
657 * -EFAULT: error copying the memory between kernel and userspace.
678 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
686 * - %DRM_XE_DEVICE_QUERY_ENGINES
687 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
688 * - %DRM_XE_DEVICE_QUERY_CONFIG
689 * - %DRM_XE_DEVICE_QUERY_GT_LIST
690 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
694 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
695 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
696 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS
702 * IOCTL call returns -EINVAL.
707 * .. code-block:: C
720 * for (int i = 0; i < engines->num_engines; i++) {
722 * engines->engines[i].instance.engine_class ==
724 * engines->engines[i].instance.engine_class ==
726 * engines->engines[i].instance.engine_class ==
728 * engines->engines[i].instance.engine_class ==
730 * engines->engines[i].instance.engine_class ==
765 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
769 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object
774 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
775 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
778 * for small-bar systems (on full-bar systems this gets turned into a
785 * Note2: For clear-color CCS surfaces the kernel needs to read the
786 * clear-color value stored in the buffer, and on discrete platforms we
789 * small-bar systems.
792 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
795 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
803 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
819 * @size: Size of the object to be created, must match region
825 * @placement: A mask of memory instances of where BO can be placed.
826 * Each index in this mask refers directly to the struct
837 * @flags: Flags, currently a mask of memory instances of where BO can
867 * between GPU- and CPU is guaranteed. The caching mode of
868 * existing CPU-mappings will be updated transparently to
869 * user-space clients.
880 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
883 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset
897 * .. code-block:: C
927 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
930 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
935 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
939 * DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is,
941 * LR VMs can be created in recoverable page-fault mode using
944 * different per-VM overcommit semantics that are enabled by
947 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
949 * demand when accessed, and also allows per-VM overcommit of memory.
971 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
985 * struct drm_xe_vm_bind_op - run bind operations
988 * - %DRM_XE_VM_BIND_OP_MAP
989 * - %DRM_XE_VM_BIND_OP_UNMAP
990 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
991 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
992 * - %DRM_XE_VM_BIND_OP_PREFETCH
995 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
997 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
999 * fault handler. This is implied on a non-faulting VM as there is no
1001 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
1007 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP,
1010 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is
1016 * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
1032 * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
1055 * there is a mismatch (see note below for pre-MTL platforms).
1057 * Note: On pre-MTL platforms there is only a caching mode and no
1059 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
1064 * levels into the following coherency buckets on all pre-MTL platforms:
1066 * ppGTT UC -> COH_NONE
1067 * ppGTT WC -> COH_NONE
1068 * ppGTT WT -> COH_NONE
1069 * ppGTT WB -> COH_AT_LEAST_1WAY
1072 * such platforms (or perhaps in general for dma-buf if shared with
1075 * have a shared-LLC. On MTL+ this completely changes and the HW
1079 * Note: For userptr and externally imported dma-buf the kernel expects
1140 #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1
1143 * It is a region instance, not a mask.
1156 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
1163 * .. code-block:: C
1227 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
1233 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority.
1235 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice
1237 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
1246 * before PXP is ready, the ioctl will return -EBUSY if init is still in
1247 * progress or -EIO if init failed.
1248 * Given that going into a power-saving state kills PXP HWDRM sessions,
1256 * .. code-block:: C
1311 * @instances: user pointer to a 2-d array of struct
1324 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
1338 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
1341 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
1362 * struct drm_xe_sync - sync object
1365 * - %DRM_XE_SYNC_TYPE_SYNCOBJ
1366 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
1367 * - %DRM_XE_SYNC_TYPE_USER_FENCE
1370 * - %DRM_XE_SYNC_FLAG_SIGNAL
1374 * .. code-block:: C
1436 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
1443 * .. code-block:: C
1475 * @num_batch_buffer: number of batch buffer in this exec, must match
1488 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
1490 * Wait on user fence, XE will wake-up on every HW engine interrupt in the
1493 * (*addr & MASK) OP (VALUE & MASK)
1498 * - %DRM_XE_UFENCE_WAIT_OP_EQ
1499 * - %DRM_XE_UFENCE_WAIT_OP_NEQ
1500 * - %DRM_XE_UFENCE_WAIT_OP_GT
1501 * - %DRM_XE_UFENCE_WAIT_OP_GTE
1502 * - %DRM_XE_UFENCE_WAIT_OP_LT
1503 * - %DRM_XE_UFENCE_WAIT_OP_LTE
1506 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
1507 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
1509 * The @mask values can be for example:
1510 * - 0xffu for u8
1511 * - 0xffffu for u16
1512 * - 0xffffffffu for u32
1513 * - 0xffffffffffffffffu for u64
1543 /** @mask: comparison mask */
1544 __u64 mask;
1573 * enum drm_xe_observation_type - Observation stream types
1576 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
1578 /** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */
1583 * enum drm_xe_observation_op - Observation stream ops
1586 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */
1589 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */
1592 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */
1597 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
1600 * multiple types. The actual params for a particular stream operation are
1607 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */
1609 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */
1611 /** @param: Pointer to actual stream params */
1616 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
1619 * ioctl's is stream type specific
1622 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */
1625 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */
1628 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */
1631 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */
1634 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */
1639 * enum drm_xe_oa_unit_type - OA unit types
1644 * sub-types of OAG. For OAR/OAC, use OAG.
1656 * struct drm_xe_oa_unit - describe OA unit
1668 /** @capabilities: OA capabilities bit-mask */
1690 * struct drm_xe_query_oa_units - describe OA units
1699 * .. code-block:: C
1706 * poau = (u8 *)&qoa->oa_units[0];
1707 * for (int i = 0; i < qoa->num_oa_units; i++) {
1710 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
1729 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
1748 * enum drm_xe_oa_property_id - OA stream property id's
1750 * Stream params are specified as a chain of @drm_xe_ext_set_property
1756 * Exactly the same mechanism is also used for stream reconfiguration using the
1757 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
1758 * subset of properties below can be specified for stream reconfiguration.
1764 * the OA stream, see @oa_unit_id in 'struct
1771 * OA unit reports or stream samples in a global buffer attached to an
1803 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE).
1808 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
1821 * to be disabled for the stream exec queue.
1857 * struct drm_xe_oa_config - OA metric configuration
1860 * particular config can be specified when opening an OA stream using
1867 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
1881 * struct drm_xe_oa_stream_status - OA stream status returned from
1882 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
1883 * call the ioctl to query stream status in response to EIO errno from
1890 /** @oa_status: OA stream status (see Bspec 46717/61226) */
1902 * struct drm_xe_oa_stream_info - OA stream info returned from
1903 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
1917 * enum drm_xe_pxp_session_type - Supported PXP session types.
1937 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
1946 * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
1973 * struct drm_xe_query_eu_stall - Information about EU stall sampling.
1983 /** @capabilities: EU stall capabilities bit-mask */
2008 * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE
2015 * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.
2016 * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.
2017 * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.
2021 * .. code-block:: C
2060 * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc
2061 * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc
2064 * - DRM_XE_MIGRATE_ALL_PAGES
2065 * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES
2069 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1
2091 * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour.
2094 * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.
2095 * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.
2096 * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.
2135 * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS
2193 * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES
2206 * If second call fails with -ENOSPC, it means memory ranges changed between
2213 * .. code-block:: C