Lines Matching +full:smem +full:- +full:part
1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
81 * - &DRM_IOCTL_XE_EXEC
82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE
83 * - &DRM_IOCTL_XE_OBSERVATION
84 * - &DRM_IOCTL_XE_MADVISE
85 * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
110 /* Must be kept compact -- no holes */
147 * .. code-block:: C
168 * struct drm_xe_user_extension - Base class for defining a chain of extensions
198 * struct drm_xe_ext_set_property - Generic set property extension
221 * struct drm_xe_engine_class_instance - instance of an engine class
223 * It is returned as part of the @drm_xe_engine, but it also is used as
228 * - %DRM_XE_ENGINE_CLASS_RENDER
229 * - %DRM_XE_ENGINE_CLASS_COPY
230 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
231 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
232 * - %DRM_XE_ENGINE_CLASS_COMPUTE
233 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
255 * struct drm_xe_engine - describe hardware engine
266 * struct drm_xe_query_engines - describe engines
282 * enum drm_xe_memory_class - Supported memory classes.
296 * struct drm_xe_mem_region - Describes some region as known to
313 * @min_page_size: Min page-size in bytes for this region.
322 * Affected IOCTLS will return %-EINVAL if alignment restrictions are
343 * any) will not be CPU accessible. If the CPU accessible part
372 * struct drm_xe_query_mem_regions - describe memory regions
388 * struct drm_xe_query_config - describe the device configuration
395 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
397 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
400 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
402 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device
404 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
406 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
408 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
409 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
432 * struct drm_xe_gt - describe an individual GT.
440 * - %DRM_XE_QUERY_GT_TYPE_MAIN
441 * - %DRM_XE_QUERY_GT_TYPE_MEDIA
491 * struct drm_xe_query_gt_list - A list with GT description items.
507 * struct drm_xe_query_topology_mask - describe the topology mask of a GT
517 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
522 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
527 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type
530 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
536 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
558 /** @mask: little-endian mask of @num_bytes */
563 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
614 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
617 * of the micro-controller firmware.
620 /** @uc_type: The micro-controller type to query firmware version */
645 * struct drm_xe_query_pxp_status - query if PXP is ready
654 * -ENODEV: PXP not supported or disabled;
655 * -EIO: fatal error occurred during init, so PXP will never be enabled;
656 * -EINVAL: incorrect value provided as part of the query;
657 * -EFAULT: error copying the memory between kernel and userspace.
678 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
686 * - %DRM_XE_DEVICE_QUERY_ENGINES
687 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
688 * - %DRM_XE_DEVICE_QUERY_CONFIG
689 * - %DRM_XE_DEVICE_QUERY_GT_LIST
690 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
694 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
695 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
696 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS
702 * IOCTL call returns -EINVAL.
707 * .. code-block:: C
720 * for (int i = 0; i < engines->num_engines; i++) {
722 * engines->engines[i].instance.engine_class ==
724 * engines->engines[i].instance.engine_class ==
726 * engines->engines[i].instance.engine_class ==
728 * engines->engines[i].instance.engine_class ==
730 * engines->engines[i].instance.engine_class ==
765 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
769 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object
774 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
779 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
781 * will always use the CPU accessible part of VRAM. This is important
782 * for small-bar systems (on full-bar systems this gets turned into a
786 * available in the CPU accessible part of VRAM (giving the same
789 * Note2: For clear-color CCS surfaces the kernel needs to read the
790 * clear-color value stored in the buffer, and on discrete platforms we
793 * small-bar systems.
796 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
799 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
807 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
871 * between GPU- and CPU is guaranteed. The caching mode of
872 * existing CPU-mappings will be updated transparently to
873 * user-space clients.
884 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
887 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset
901 * .. code-block:: C
931 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
934 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
939 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
943 * DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is,
945 * LR VMs can be created in recoverable page-fault mode using
948 * different per-VM overcommit semantics that are enabled by
951 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
953 * demand when accessed, and also allows per-VM overcommit of memory.
975 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
989 * struct drm_xe_vm_bind_op - run bind operations
992 * - %DRM_XE_VM_BIND_OP_MAP
993 * - %DRM_XE_VM_BIND_OP_UNMAP
994 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
995 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
996 * - %DRM_XE_VM_BIND_OP_PREFETCH
999 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
1001 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
1003 * fault handler. This is implied on a non-faulting VM as there is no
1005 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
1011 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP,
1014 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is
1020 * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
1036 * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
1059 * there is a mismatch (see note below for pre-MTL platforms).
1061 * Note: On pre-MTL platforms there is only a caching mode and no
1063 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
1068 * levels into the following coherency buckets on all pre-MTL platforms:
1070 * ppGTT UC -> COH_NONE
1071 * ppGTT WC -> COH_NONE
1072 * ppGTT WT -> COH_NONE
1073 * ppGTT WB -> COH_AT_LEAST_1WAY
1076 * such platforms (or perhaps in general for dma-buf if shared with
1079 * have a shared-LLC. On MTL+ this completely changes and the HW
1080 * defines the coherency mode as part of the @pat_index, where
1083 * Note: For userptr and externally imported dma-buf the kernel expects
1144 #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1
1160 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
1167 * .. code-block:: C
1231 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
1237 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority.
1239 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice
1241 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
1250 * before PXP is ready, the ioctl will return -EBUSY if init is still in
1251 * progress or -EIO if init failed.
1252 * Given that going into a power-saving state kills PXP HWDRM sessions,
1260 * .. code-block:: C
1315 * @instances: user pointer to a 2-d array of struct
1328 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
1342 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
1345 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
1366 * struct drm_xe_sync - sync object
1369 * - %DRM_XE_SYNC_TYPE_SYNCOBJ
1370 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
1371 * - %DRM_XE_SYNC_TYPE_USER_FENCE
1374 * - %DRM_XE_SYNC_FLAG_SIGNAL
1378 * .. code-block:: C
1440 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
1447 * .. code-block:: C
1492 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
1494 * Wait on user fence, XE will wake-up on every HW engine interrupt in the
1502 * - %DRM_XE_UFENCE_WAIT_OP_EQ
1503 * - %DRM_XE_UFENCE_WAIT_OP_NEQ
1504 * - %DRM_XE_UFENCE_WAIT_OP_GT
1505 * - %DRM_XE_UFENCE_WAIT_OP_GTE
1506 * - %DRM_XE_UFENCE_WAIT_OP_LT
1507 * - %DRM_XE_UFENCE_WAIT_OP_LTE
1510 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
1511 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
1514 * - 0xffu for u8
1515 * - 0xffffu for u16
1516 * - 0xffffffffu for u32
1517 * - 0xffffffffffffffffu for u64
1577 * enum drm_xe_observation_type - Observation stream types
1587 * enum drm_xe_observation_op - Observation stream ops
1601 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
1620 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
1643 * enum drm_xe_oa_unit_type - OA unit types
1648 * sub-types of OAG. For OAR/OAC, use OAG.
1660 * struct drm_xe_oa_unit - describe OA unit
1672 /** @capabilities: OA capabilities bit-mask */
1694 * struct drm_xe_query_oa_units - describe OA units
1703 * .. code-block:: C
1710 * poau = (u8 *)&qoa->oa_units[0];
1711 * for (int i = 0; i < qoa->num_oa_units; i++) {
1714 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
1733 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
1752 * enum drm_xe_oa_property_id - OA stream property id's
1861 * struct drm_xe_oa_config - OA metric configuration
1871 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
1885 * struct drm_xe_oa_stream_status - OA stream status returned from
1906 * struct drm_xe_oa_stream_info - OA stream info returned from
1921 * enum drm_xe_pxp_session_type - Supported PXP session types.
1941 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
1977 * struct drm_xe_query_eu_stall - Information about EU stall sampling.
1987 /** @capabilities: EU stall capabilities bit-mask */
2012 * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE
2019 * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.
2020 * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.
2021 * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.
2025 * .. code-block:: C
2064 * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc
2065 * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc
2068 * - DRM_XE_MIGRATE_ALL_PAGES
2069 * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES
2073 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1
2095 * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour.
2098 * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.
2099 * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.
2100 * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.
2139 * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS
2197 * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES
2210 * If second call fails with -ENOSPC, it means memory ranges changed between
2217 * .. code-block:: C