Lines Matching refs:__u64
191 __u64 bo_size;
193 __u64 alignment;
195 __u64 domains;
197 __u64 domain_flags;
228 __u64 bo_info_ptr;
316 __u64 flags;
383 __u64 queue_va;
388 __u64 queue_size;
393 __u64 rptr_va;
401 __u64 wptr_va;
410 __u64 mqd;
416 __u64 mqd_size;
441 __u64 shadow_va;
446 __u64 csa_va;
456 __u64 csa_va;
466 __u64 eop_va;
481 __u64 syncobj_handles;
486 __u64 num_syncobj_handles;
491 __u64 bo_read_handles;
496 __u64 bo_write_handles;
514 __u64 va;
520 __u64 value;
534 __u64 syncobj_handles;
539 __u64 syncobj_timeline_handles;
544 __u64 syncobj_timeline_points;
549 __u64 bo_read_handles;
554 __u64 bo_write_handles;
585 __u64 out_fences;
600 __u64 flags;
636 __u64 addr;
637 __u64 size;
697 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
699 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
712 __u64 flags;
714 __u64 tiling_info;
728 __u64 addr_ptr;
742 __u64 timeout;
762 __u64 handle;
764 __u64 timeout;
773 __u64 status;
786 __u64 seq_no;
791 __u64 fences;
794 __u64 timeout_ns;
813 __u64 addr;
816 __u64 size;
819 __u64 offset;
822 __u64 flags;
832 __u64 value;
843 __u64 entries;
859 __u64 size;
862 __u64 preferred_domains;
865 __u64 alloc_flags;
868 __u64 alignment;
914 __u64 va_address;
916 __u64 offset_in_bo;
918 __u64 map_size;
922 __u64 vm_timeline_point;
931 __u64 input_fence_syncobj_handles;
966 __u64 chunk_data;
977 __u64 chunks;
981 __u64 handle;
1022 __u64 va_start;
1038 __u64 handle;
1053 __u64 point;
1081 __u64 shadow_va;
1082 __u64 csa_va;
1083 __u64 gds_va;
1084 __u64 flags;
1301 __u64 return_pointer;
1369 __u64 vram_size;
1370 __u64 vram_cpu_accessible_size;
1371 __u64 gtt_size;
1376 __u64 total_heap_size;
1379 __u64 usable_heap_size;
1387 __u64 heap_usage;
1393 __u64 max_allocation;
1444 __u64 max_engine_clock;
1445 __u64 max_memory_clock;
1457 __u64 ids_flags;
1459 __u64 virtual_address_offset;
1461 __u64 virtual_address_max;
1478 __u64 prim_buf_gpu_addr;
1480 __u64 pos_buf_gpu_addr;
1482 __u64 cntl_sb_buf_gpu_addr;
1484 __u64 param_buf_gpu_addr;
1508 __u64 high_va_offset;
1510 __u64 high_va_max;
1514 __u64 tcc_disabled_mask;
1515 __u64 min_engine_clock;
1516 __u64 min_memory_clock;
1524 __u64 mall_size; /* AKA infinity cache */
1545 __u64 capabilities_flags;
1616 __u64 addr;