Lines Matching +full:enable +full:- +full:bias +full:- +full:control

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 /* Used to enable configuration of a GPIO to all zeros */
17  * R6 (0x06) - Mic Bias Control 0
19 #define WM8904_MICDET_THR_MASK                  0x0070  /* MICDET_THR - [6:4] */
20 #define WM8904_MICDET_THR_SHIFT                      4  /* MICDET_THR - [6:4] */
21 #define WM8904_MICDET_THR_WIDTH                      3  /* MICDET_THR - [6:4] */
22 #define WM8904_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
23 #define WM8904_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
24 #define WM8904_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
35  * R7 (0x07) - Mic Bias Control 1
45 #define WM8904_MICBIAS_SEL_MASK                 0x0007  /* MICBIAS_SEL - [2:0] */
46 #define WM8904_MICBIAS_SEL_SHIFT                     0  /* MICBIAS_SEL - [2:0] */
47 #define WM8904_MICBIAS_SEL_WIDTH                     3  /* MICBIAS_SEL - [2:0] */
51  * R121 (0x79) - GPIO Control 1
61 #define WM8904_GPIO1_SEL_MASK                   0x000F  /* GPIO1_SEL - [3:0] */
62 #define WM8904_GPIO1_SEL_SHIFT                       0  /* GPIO1_SEL - [3:0] */
63 #define WM8904_GPIO1_SEL_WIDTH                       4  /* GPIO1_SEL - [3:0] */
66  * R122 (0x7A) - GPIO Control 2
76 #define WM8904_GPIO2_SEL_MASK                   0x000F  /* GPIO2_SEL - [3:0] */
77 #define WM8904_GPIO2_SEL_SHIFT                       0  /* GPIO2_SEL - [3:0] */
78 #define WM8904_GPIO2_SEL_WIDTH                       4  /* GPIO2_SEL - [3:0] */
81  * R123 (0x7B) - GPIO Control 3
91 #define WM8904_GPIO3_SEL_MASK                   0x000F  /* GPIO3_SEL - [3:0] */
92 #define WM8904_GPIO3_SEL_SHIFT                       0  /* GPIO3_SEL - [3:0] */
93 #define WM8904_GPIO3_SEL_WIDTH                       4  /* GPIO3_SEL - [3:0] */
96  * R124 (0x7C) - GPIO Control 4
110 #define WM8904_GPIO_BCLK_SEL_MASK               0x000F  /* GPIO_BCLK_SEL - [3:0] */
111 #define WM8904_GPIO_BCLK_SEL_SHIFT                   0  /* GPIO_BCLK_SEL - [3:0] */
112 #define WM8904_GPIO_BCLK_SEL_WIDTH                   4  /* GPIO_BCLK_SEL - [3:0] */
121  * values to write (the enable bits will be ignored).  At runtime an
122  * enumerated control will be presented for each DRC block allowing
125  * Configurations may be generated by hand or by using the DRC control
126  * panel provided by the WISCE - see  http://www.wolfsonmicro.com/wisce/
136  * rate and set of values to write (the enable bits will be ignored).
139  * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/