Lines Matching full:aes3
56 #define CS8427_MMR (1<<3) /* AES3 receiver operation, 0 = stereo, 1 = mono */
57 #define CS8427_MMT (1<<2) /* AES3 transmitter operation, 0 = stereo, 1 = mono */
62 #define CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
64 #define CS8427_TXDMASK (3<<3) /* AES3 Transmitter Data Source Mask */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
81 #define CS8427_RXDAES3INPUT (1<<0) /* 256*Fsi from AES3 input */
100 #define CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */
104 #define CS8427_SORESDIRECT (2<<4) /* SIRES direct copy from AES3 receiver */
111 #define CS8427_TSLIP (1<<7) /* AES3 transmitter source data slip interrupt */
161 #define CS8427_UBMMASK (3<<2) /* Operating mode of the AES3 U bit manager */