Lines Matching +full:timer +full:- +full:dsp

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define CS4231_PLAYBK_FORMAT	0x08	/* clock and data format - playback - bits 7-0 MCE */
30 #define CS4231_IFACE_CTRL	0x09	/* interface control - bits 7-2 MCE */
43 #define CS4231_TIMER_LOW	0x14	/* timer low byte */
44 #define CS4231_TIMER_HIGH	0x15	/* timer high byte */
52 #define CS4231_VERSION		0x19	/* CS4231(A) - version values */
57 #define CS4231_REC_FORMAT	0x1c	/* clock and data format - record - bits 7-0 MCE */
63 /* definitions for codec register select port - CODECP( REGSEL ) */
69 /* definitions for codec status register - CODECP( STATUS ) */
93 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
95 #define CS4231_LINEAR_8		0x00	/* 8-bit unsigned data */
96 #define CS4231_ALAW_8		0x60	/* 8-bit A-law companded */
97 #define CS4231_ULAW_8		0x20	/* 8-bit U-law companded */
98 #define CS4231_LINEAR_16	0x40	/* 16-bit twos complement data - little endian */
99 #define CS4231_LINEAR_16_BIG	0xc0	/* 16-bit twos complement data - big endian */
100 #define CS4231_ADPCM_16		0xa0	/* 16-bit ADPCM */
102 /* bits 3-1 define frequency divisor */
106 /* definitions for interface control register - CS4231_IFACE_CTRL */
116 /* definitions for pin control register - CS4231_PIN_CTRL */
122 /* definitions for test and init register - CS4231_TEST_INIT */
127 /* definitions for misc control register - CS4231_MISC_INFO */
130 #define CS4231_IW_MODE3		0x6c	/* MODE 3 - InterWave enhanced mode */
131 #define CS4231_4236_MODE3	0xe0	/* MODE 3 - CS4236+ enhanced mode */
133 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
136 #define CS4231_TIMER_ENABLE	0x40	/* codec timer enable */
139 /* definitions for Extended Registers - CS4236+ */
152 #define CS4236_LEFT_DSP		0x88	/* left DSP serial port volume */
153 #define CS4236_RIGHT_DSP	0x98	/* right DSP serial port volume */
164 /* definitions for extended registers - OPTI93X */