Lines Matching +full:clock +full:- +full:detection +full:- +full:disable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4117_REG_CLOCK 0x01 /* clock control */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
36 #define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */
39 #define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
40 #define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
43 #define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */
44 #define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
45 #define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
55 #define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */
61 #define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */
69 #define AK4117_CM_PLL (0) /* use RX input as master clock */
70 #define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */
72 #define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for mon…
76 #define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */
87 #define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */
88 #define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */
89 #define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */
90 #define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */
91 #define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */
107 #define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
109 #define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */
110 #define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect …
112 #define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
115 #define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
116 #define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
117 #define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */
118 #define AK4117_FS3 (1<<3) /* sampling frequency detection */
132 #define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */