Lines Matching +full:8 +full:bit
13 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14 #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
16 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
19 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
20 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
21 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
57 #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
58 #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
64 #define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
65 #define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
66 #define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
103 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
104 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
105 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
129 #define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
136 #define QSYS_SE_CFG_SE_RR_ENA BIT(5)
137 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
141 #define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
142 #define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
155 #define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
156 #define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
157 #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
161 #define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
174 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
175 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
176 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
193 #define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
195 #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
199 #define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
200 #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
201 #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
205 #define QSYS_TAG_CONFIG_ENABLE BIT(0)
209 #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
210 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
211 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
218 #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
219 #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
231 #define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
232 #define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
233 #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
246 #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
250 #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
251 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
252 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)