Lines Matching +full:9 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
110 #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
111 #define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
112 #define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
113 #define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
117 #define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
118 #define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
119 #define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
120 #define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
121 #define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
122 #define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
124 #define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
125 #define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
126 #define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
127 #define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
128 #define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
129 #define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
130 #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
134 #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
135 #define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
136 #define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
137 #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
138 #define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
139 #define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
140 #define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
141 #define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
142 #define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
143 #define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
144 #define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
145 #define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
146 #define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
147 #define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
155 #define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
156 #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
157 #define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
158 #define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
159 #define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
160 #define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
161 #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
162 #define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
163 #define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
164 #define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
165 #define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
181 #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
185 #define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
192 #define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
193 #define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
197 #define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
198 #define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
199 #define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
200 #define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
204 #define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
218 #define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
220 #define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
221 #define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
234 #define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
235 #define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
236 #define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
244 #define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
245 #define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
249 #define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
250 #define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
251 #define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
252 #define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
256 #define HSIO_RCOMP_STATUS_BUSY BIT(12)
257 #define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
269 #define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
271 #define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
285 #define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
289 #define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
291 #define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
298 #define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
299 #define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
300 #define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
301 #define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
302 #define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
303 #define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
322 #define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
323 #define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
330 #define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
331 #define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
332 #define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
333 #define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
337 #define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
338 #define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
339 #define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
340 #define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
342 #define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
343 #define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
344 #define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
345 #define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
346 #define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
350 #define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
351 #define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
352 #define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
353 #define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
354 #define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
355 #define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
356 #define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
358 #define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
359 #define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
363 #define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
364 #define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
365 #define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
366 #define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
368 #define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
369 #define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
370 #define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
374 #define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
375 #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
382 #define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
383 #define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
384 #define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
385 #define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
393 #define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
394 #define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
395 #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
396 #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
404 #define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
405 #define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
406 #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
407 #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
409 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
422 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
423 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
424 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
425 #define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
426 #define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
427 #define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
428 #define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
429 #define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
431 #define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
432 #define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
433 #define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
434 #define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
435 #define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
436 #define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
437 #define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
439 #define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
441 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
442 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
449 #define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
450 #define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
457 #define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
458 #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
465 #define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
466 #define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
467 #define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
468 #define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
476 #define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
477 #define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
478 #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
479 #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
487 #define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
488 #define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
489 #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
490 #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
492 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
508 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
509 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
510 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
511 #define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
512 #define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
513 #define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
514 #define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
515 #define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
516 #define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
517 #define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
534 #define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
535 #define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
536 #define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
537 #define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
538 #define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
539 #define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
540 #define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
541 #define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
543 #define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
551 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
552 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
553 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
557 #define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
561 #define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
566 #define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
585 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
586 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
587 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
591 #define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
592 #define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
593 #define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
594 #define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
595 #define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
596 #define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
597 #define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
608 #define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
609 #define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
610 #define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
611 #define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
612 #define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
613 #define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
614 #define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
615 #define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
632 #define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
633 #define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
634 #define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
677 #define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
678 #define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
679 #define HSIO_S6G_OB_CFG_OB_POL BIT(29)
686 #define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
687 #define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
691 #define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
692 #define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
693 #define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
706 #define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
707 #define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
708 #define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
712 #define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
713 #define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
714 #define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
715 #define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
717 #define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
718 #define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
719 #define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
720 #define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
721 #define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
722 #define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
723 #define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
724 #define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
725 #define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
726 #define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
727 #define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
728 #define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
729 #define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
730 #define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
731 #define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
732 #define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
739 #define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
740 #define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
744 #define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
745 #define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
746 #define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
747 #define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
748 #define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
749 #define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
751 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
752 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
753 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
754 #define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
755 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
756 #define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
764 #define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
765 #define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
766 #define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
767 #define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
768 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
769 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
770 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
771 #define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
772 #define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
786 #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
787 #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
788 #define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
790 #define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
791 #define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
792 #define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
808 #define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
809 #define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
810 #define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
814 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
815 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
819 #define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
820 #define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
821 #define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
822 #define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
823 #define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
824 #define HSIO_HW_CFG_PCIE_ENA BIT(1)
825 #define HSIO_HW_CFG_QSGMII_ENA BIT(0)
827 #define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
828 #define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
829 #define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
830 #define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
835 #define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
840 #define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
842 #define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
843 #define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
844 #define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
845 #define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
846 #define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
847 #define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
855 #define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)